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configurable Enterprise:A New Trend in Manufacturing Enterprise Evolution

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武汉理工大学学报 2006年第S3期28卷 882-886页

作者： GU Yuanxun GUO Jingjuan School of Economics and Management,Beijing Jiaotong University,Beijing 100044,China School of Economics and Management Beijing Jiaotong UniversityBeijing 100044China

Along with the popularity of enterprise applications,the management reform of manufacturing enterprise(ME) relies on the business process reengineering is gradually *** and comparison the former structure of different enter- prise such as extend enterprise,virtual enterprise *** the perspective of link,unit,and *** comparison the evo- lution of ME structure the configurable enterprise(CE)was put forward which based on the information and communication tech- nology providing a new mechanism for the elements configuration and the resources *** on the reference model of en- terprise business architecture,the framework of CE was raised,which includes enterprise business architecture,business model and *** modeling the dynamics of CE,the mechanism of key success factors interactions was analyzed and verified the key factors that de decided the evolution of CE which could forecast the development trend of manufacturing enterprise.

关键词： configurable enterprise enterprise business architecture business component evolution

GERO: a general SCA-based readout ASIC for micro-pattern gas detectors with configurable storage depth and on-chip digitizer

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Nuclear Science and Techniques 2019年第9期30卷 1-8页

作者： Xin-Yuan Zhao Feng Liu Zhi Deng Yi-Nong Liu The Department of Engineering Physics Tsinghua University Beijing 100084 China The Key Laboratory of Particle and Radiation Imaging (Tsinghua University) Ministry of Education Beijing 100084 China

The paper presents GEneral ReadOut (GERO), a general readout ASIC based on a switched capacitor array for micro-pattern gas detectors. It aims at providing general readout electronics for low-to-medium event-rate gas detectors with high sampling frequency, configurable storage depth, and data digitalization. The first prototype GERO chip integrates 16 channels and was fabricated using a 0.18-lm CMOS process. Each channel consists of a sampling array working in a ping-pong mode, a storage array with a 1024-cell depth, and 32 Wilkinson analog-todigital converters. The detailed design and test results are presented in the paper.

关键词： ASIC Switched capacitor array Waveform sampling configurable deep memory depth

A Novel configurable Boundary-scan Circuit Design of SRAM-Based FPGA

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A Novel Configurable Boundary-scan Circuit Design of SRAM-Ba...

An Elastic Architecture Adaptable to Various Application Scenarios

2011 IEEE International Conference on Computer Science and Automation Engineering(CSAE 2011)

作者： Chenguang Guo Yanlong Zhang Zhiping Wen Lei Chen Xuewu Li Zengrong Liu Min Wang Beijing Microelectronics Tech.Institution (BMTI) Beijing China

This paper presents a novel configurable boundaryscan circuit （CBSC） of SRAM-based field programmable gate array （FPGA）.The embedded SRAM cells of FPGA have been used to modify the original structure of boundary-scan circuit （BSC）.Users only need to change the data stored in the embedded SRAM cell during the configuration of the FPGA *** this way,the boundary-scan chain can be configured to any desired *** with the original structure of BSC,this circuit using 0.25μm CMOS process can be part of a standard digital cell library and has been used in the BQV series FPGAs of BMTI.

关键词： configurable Boundary-scan SRAM cell FPGA

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Journal of Computer Science & Technology 2014年第2期29卷 227-238页

作者：伍岳陈云霁陈天石郭崎张磊 State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences IBM Research-China

The quantity of computer applications is increasing dramatically as the computer industry prospers. Meanwhile, even for one application, it has different requirements of performance and power in different scenarios. Although various processors with different architectures emerge to fit for the various applications in different scenarios, it is impossible to design a dedicated processor to meet all the requirements. Furthermore, dealing with uncertain processors significantly aggravates the burden of programmers and system integrators to achieve specific performance/power. In this paper, we propose elastic architecture （EA） to provide a uniform computing platform with high elasticity, i.e., the ratio of worst-case to best-case performance/power/performance-power trade-off, which can meet different requirements for different applications. It is achieved by dynamically adjusting architecture parameters （instruction set, branch predictor, data path, memory hierarchy, concurrency, status^zcontrol, and so on） on demand. The elasticity of our prototype implementation of EA, as Sim-EA, ranges from 3.31 to 14.34, with 5.41 in arithmetic average, for SPEC CPU2000 benchmark suites, which provides great flexibility to fulfill the different performance and power requirements in different scenarios. Moreover, Sim-EA can reduce the EDP （energy-delay product） for 31.14% in arithmetic average compared with a baseline fixed architecture. Besides, some subsequent experiments indicate a negative correlation between application intervals＇ lengths and their elasticities.

关键词： architecture design configurable elasticity energy-delay product reduction

Reconfigurable Patch Bandpass Filter

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Reconfigurable Patch Bandpass Filter

2015年全国微波毫米波会议

作者： Z.W.Liu S.Y.Zheng SYSU-CMU Shunde International Joint Research Institute Department of Electronics and Communication Engineering Sun Yat-sen University

A nfigurable patch bandpass filter is demonstrated using a dual mode rectangular patch. The proposed circuit use varactor loaded patterned ground plane to control its operating frequency. The coupling gaps required in conventional dual mode bandpass filter are eliminated to maintain the simplicity imposed by patch type structure. For demonstration, a reconfigurable patch bandpass filter is designed and verified to be able to exhibit good performance over a frequency range of 20.5%（from 1.18 GHz to 1.45 GHz）.

关键词： configurable patch bandpass filter varactor loaded patterned ground plane

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统计报表可配置平台的设计与实现

统计报表可配置平台的设计与实现