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A Lock-Based cache coherence Protocol for Scope Consistency

Journal of Computer Science & Technology 1998年第2期13卷 97-109页

作者：胡伟武 *** 施巍松 *** 唐志敏 *** 李明 *** Institute of Computing Technology Chinese Academy of Sciences Beijing P.R. China

Directory protocols are widely adopted to maintain cache coherence of distributed shared memory multiprocessors. Although scalable to a certain extent, directory protocols are complex enough to prevent it from being used in very large scale multiprocessors with tens of thousands of nodes. This paper proposes a lock-based cache coherence protocol for scope conyistency. It does not rely on directory information to maintain cache coherence. Instead, cache coherence is mailltained through requiring the releasing processor of a lock to store all write-notices generated in the associated critical section to the lock and the acquiring processor invalidates or updates its locally cached data copies according to the write notices of the lock. To evaluate the performance of the lock-based cache coherence protocol, a software DSM system named JIAJIA is built on network of workstations. Besides the lockbased cache coherence protocol, JIAJIA also characterizes itself with its shared memory organization scheme which combines the physical memories of multiple workstations to form a large shared space. Performance measurements with SPLASH2 program suite and NAS benchmarks indicate that, compared to recent SVM systems such as CVM, higher speedup is achieved by ***, JIAJIA can solve large scale problems that cannot be solved by other SVM systems due to memory size limitation.

关键词： Memory consistency cache coherence lock-based protocol directorybased protocol,scope consistency

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维普期刊数据库

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NONH:A New cache-Based coherence Protocol for Linked List Structure DSM System and Its Performance Evaluation

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Journal of Computer Science & Technology 1996年第4期11卷 405-415页

作者：房至一鞠九滨 DepartmentofComputerScience JilinUniversityChangchun130023 DepartmentofComputerScience JilinUniversi

The management of memory coherence is an important problem in distributed shared memory (DSM) system. In a cache-based coherence DSM system using linked list structure, the key to maintaining the coherence and improving system performance is how to manage the owner in the linked list. This paper presents the design of a new management protocol-NONH (New-OwnerNew-Head) and its performance evaluation. The analysis results show that thisprotocol can improve the scalability and performence of a coherent DSM system using linked list. It is also suitable for managing the cache coherency in tree-like hierarchical architecture.

关键词： Linked list cache coherence distributed shared memory

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维普期刊数据库

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Improving multiprocessor performance with fine-grain coherence bypass

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Science China(Information Sciences) 2015年第1期58卷 84-98页

作者： WANG Hui WANG Rui LUAN ZhongZhi QIAN XueHai QIAN DePei Sino-German Joint Software Institute School of Computer Science and EngineeringBeihang University University of Illinois Urbana-Champaign

Efficient and scalable cache coherence protocol is crucial to high-performance servers with sharedmemory. The directory-based cache coherence protocol is more desirable than the snooping-based protocol with respect to the scalability. However, even for the former protocol, scaling to a large number of cores is also challenging due to the additional area requirements of the directories. We observed that a significant percentage of the referenced memory blocks were only accessed by a single core(even in parallel applications) which could be considered as private memory blocks. An intuitive motivation from this observation is that memory blocks accessed by a single core do not require coherence maintenance. The issue is to identify the private block and track the change of its access pattern. We propose a novel hardware approach to(1) dynamically identify the shared memory blocks at the cache block level, and(2) bypass the coherence procedure for the private memory blocks. This approach increases the effectiveness of the directory-based approach and therefore improves the system performance. Experimental results showed that, our approach can on an average(1) avoid the coherence tracking of about 54% referenced memory blocks,(2) reduce the coherence overhead by 77%,(3) avoid 8% L2 cache misses, and(4) shorten the execution time of parallel applications by 13%.

关键词： many-core cache coherence private memory block fine-grain coherence high performance

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System Architecture of Godson-3 Multi-Core Processors

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Journal of Computer Science & Technology 2010年第2期25卷 181-191页

作者：高翔陈云霁王焕东唐丹胡伟武 Institute of Computing Technology Chinese Academy of Sciences Graduate University of Chinese Academy of Sciences

Godson-3 is the latest generation of Godson microprocessor family. It takes a scalable multi-core architecture with hardware support for accelerating applications including X86 emulation and signal processing. This paper introduces the system architecture of Godson-3 from various aspects including system scalability, organization of memory hierarchy, network-on-chip, inter-chip connection and I/O subsystem.

关键词： multi-core processor scalable interconnection cache coherent non-uniform memory access/non-uniform cache access (CC-NUMA/NUCA) MESH crossbar cache coherence reliability availability and serviceability (RAS)

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