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Improving multiprocessor performance with fine-grain coherence bypass

Improving multiprocessor performance with fine-grain coherence bypass

作     者:WANG Hui WANG Rui LUAN ZhongZhi QIAN XueHai QIAN DePei 

作者机构:Sino-German Joint Software InstituteSchool of Computer Science and EngineeringBeihang University University of Illinois Urbana-Champaign 

出 版 物:《Science China(Information Sciences)》 (中国科学:信息科学(英文版))

年 卷 期:2015年第58卷第1期

页      面:84-98页

核心收录:

学科分类:08[工学] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术(可授工学、理学学位)] 

基  金:supported by National High-tech R&D Program of China (863) (Grant No. 2012AA010902) National Natural Science Foundation of China (Grant Nos. 61073011, 61133004, 61202425) 

主  题:many-core cache coherence private memory block fine-grain coherence high performance 

摘      要:Efficient and scalable cache coherence protocol is crucial to high-performance servers with sharedmemory. The directory-based cache coherence protocol is more desirable than the snooping-based protocol with respect to the scalability. However, even for the former protocol, scaling to a large number of cores is also challenging due to the additional area requirements of the directories. We observed that a significant percentage of the referenced memory blocks were only accessed by a single core(even in parallel applications) which could be considered as private memory blocks. An intuitive motivation from this observation is that memory blocks accessed by a single core do not require coherence maintenance. The issue is to identify the private block and track the change of its access pattern. We propose a novel hardware approach to(1) dynamically identify the shared memory blocks at the cache block level, and(2) bypass the coherence procedure for the private memory blocks. This approach increases the effectiveness of the directory-based approach and therefore improves the system performance. Experimental results showed that, our approach can on an average(1) avoid the coherence tracking of about 54% referenced memory blocks,(2) reduce the coherence overhead by 77%,(3) avoid 8% L2 cache misses, and(4) shorten the execution time of parallel applications by 13%.

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