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An Improved binary search Anti-Collision Protocol for RFID Tag Identification

Computers, Materials & Continua 2020年第11期65卷 1855-1868页

作者： Guozhong Dong Weizhe Zhang Sichang Xuan Feng Qin Haowen Tan The Cyberspace Security Research Center Peng Cheng LaboratoryShenzhen518000China School of Computer Science and Technology Harbin Institute of TechnologyHarbin150001China Information Security Research Center Harbin Engineering UniversityHarbin150001China Wuhan Maritime Communication Research Institute Wuhan430205China Department of Computer Engineering Chosun UniversityGwangju61452Korea

Radio frequency identification(RFID)has been widespread used in massive items tagged domains.However,tag collision increases both time and energy consumption of RFID network.Tag collision can seriously affect the success of tag identification.An efficient anti-collision protocol is very crucially in RFID system.In this paper,an improved binary search anti-collision protocol namely BRTP is proposed to cope with the tag collision concern,which introduces a Bi-response mechanism.In Bi-response mechanism,two groups of tags allowed to reply to the reader in the same slot.According to Bi-response mechanism,the BRTP strengthens the tag identification of RFID network by reducing the total number of queries and exchanged messages between the reader and tags.Both theoretical analysis and numerical results verify the effectiveness of the proposed BRTP in various performance metrics including the number of total slots,system efficiency,communication complexity and total identification time.The BRTP is suitable to be applied in passive RFID systems.

关键词： RFID anti-collision binary search Bi-response mechanism

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A high-precision synchronization circuit for clock distribution

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Journal of Semiconductors 2015年第10期36卷 108-116页

作者：路崇谭洪舟段志奎丁一 SYSU-CMU Shunde International Joint Research Institute School of Information Science and Technology Sun Yat-Sen University

In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 μm 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between [20%, 80%]. The active area of the core circuits is 245 × 134 μm2, and the power consumption is 1.64 mW at 500 MHz.

关键词： HPSC clock synchronization circuit SMD dynamic compensation circuit binary search interleaveddelay units

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Inverse Generalized Minimum Cost Flow Problem Under the Hamming Distances

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Journal of the Operations Research Society of China 2019年第2期7卷 355-364页

作者： Mobarakeh Karimi Massoud Aman Ardeshir Dolati Faculty of Mathematics and Statistics University of BirjandBirjandIran Department of Computer Science Shahed UniversityTehranIran

Given a generalized minimum cost flow problem,the corresponding inverse problem is to find a minimal adjustment of the cost function so that the given generalized flow becomes optimal to the problem.In this paper,we consider both types of the weighted Hamming distances for measuring the adjustment.In the sum-type case,it is shown that the inverse problem is APX-hard.In the bottleneck-type case,we present a polynomial time algorithm.

关键词： Generalized minimum cost flow Inverse problem Hamming distance binary search

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Blocking optimized SIMD tree search on modern processors

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Journal of Shanghai University(English Edition) 2011年第5期15卷 437-444页

作者：张倬陆宇凡沈文枫徐炜民郑衍衡 School of Computer Engineering and Science Shanghai University

Tree search is a widely used fundamental algorithm. Modern processors provide tremendous computing power by integrating multiple cores, each with a vector processing unit. This paper reviews some studies on exploiting single instruction multiple date （SIMD） capacity of processors to improve the performance of tree search, and proposes several improvement methods on reported SIMD tree search algorithms. Based on blocking tree structure, blocking for memory alignment and dynamic blocking prefetch are proposed to optimize the overhead of memory access. Furthermore, as a way of non-linear loop unrolling, the search branch unwinding shows that the number of branches can exceed the data width of SIMD instructions in the SIMD search algorithm. The experiments suggest that blocking optimized SIMD tree search algorithm can achieve 1.6 times response speed faster than the un-optimized algorithm.

关键词： single instruction multiple date （SIMD） tree search binary search streaming SIMD extensions （SSE） Cell broadband engine （BE）

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