A high-precision synchronization circuit for clock distribution

作     者：路崇 谭洪舟 段志奎 丁一 

作者机构：SYSU-CMU Shunde International Joint Research Institute School of Information Science and TechnologySun Yat-Sen University 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2015年第36卷第10期

页      面：108-116页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0805[工学-材料科学与工程（可授工学、理学学位）] 0703[理学-化学] 0702[理学-物理学] 

主　　题：HPSC clock synchronization circuit SMD dynamic compensation circuit binary search interleaveddelay units 

摘      要：In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 μm 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between [20%, 80%]. The active area of the core circuits is 245 × 134 μm2, and the power consumption is 1.64 mW at 500 MHz.