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Design and Optimization of a Low-Noise voltage reference Using Chopper Stabilization Technique

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Chinese Journal of Electronics 2017年第5期26卷 981-985页

作者： PENG Lingjie JIN Xiangliang LIU Mengliang School of Physics and Optoelectronics Xiangtan University Hunan Engineering Laboratory for Microelectronics Optoelectronics and System on a Chip

A low-noise voltage reference is presented to enhance resolution of MEMS capacitive accelerometer and reduce system noise,in which the circuit uses Chopper stabilization(CHS) technique for the suppression of low-frequency noise.A 3.7V voltage reference chip is fabricated in a 0.5-μm CMOS *** with the voltage reference without using CHS,the proposed design is much more superior in low-noise *** results indicate that the output noise of reference voltage V RP can reach 0.121μV/sqrt(Hz) at the vicinity of 3 Hz.

关键词： voltage reference Low noise Chopper stabilization Amplifier

An inherent curvature-compensated voltage reference using non-linearity of gate coupling coefficient

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Journal of Semiconductors 2015年第8期36卷 113-123页

作者： Vinayak Hande Maryam Shojaei Baghini Indian Institute of Technology Bombay

A novel current-mode voltage reference circuit which is capable of generating sub- 1 V output voltage is presented. The proposed architecture exhibits the inherent curvature compensation ability. The curvature com- pensation is achieved by utilizing the non-linear behavior of gate coupling coefficient to compensate non-linear temperature dependence of base-emitter voltage. We have also utilized the developments in CMOS process to re- duce power and area consumption. The proposed voltage reference is analyzed theoretically and compared with other existing methods. The circuit is designed and simulated in 180 nm mixed-mode CMOS UMC technology which gives a reference level of 246 mV. The minimum required supply voltage is 1 V with maximum current drawn of 9.24μA. A temperature coefficient of 9 ppm/℃ is achieved over -25 to 125 ℃ temperature range. The reference voltage varies by ±11 mV across process corners. The reference circuit shows the line sensitivity of 0.9 mV/V with area consumption of 100 × ll0μm2

关键词： voltage reference gate coupling coefficient temperature coefficient curvature compensation

A new curvature compensation technique for CMOS voltage reference using |V_(GS)| and △V_(BE)

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Journal of Semiconductors 2016年第5期37卷 97-103页

作者：李雪民叶茂赵公元张赟赵毅强 School of Electronic Information and Engineering Tianjin University

A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate voltage｜VGS｜p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate-source voltages｜VGS｜n of NMOS transistors in the subthreshold region and the difference between two base-emitter voltages △VBE of bipolar junction transistors （BJTs）. The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area. The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 pprrd /℃ without trimming, over a temperature range from -40 to 120℃, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio （PSRR） is -31.2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm2.

关键词： voltage reference sub-reference curvature compensation subthreshold

A 150-nA 13.4-ppm/℃switched-capacitor CMOS sub-bandgap voltage reference

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Journal of Semiconductors 2011年第4期32卷 155-160页

作者：严伟李文宏刘冉 State Key Laboratory of ASIC & Systems Fudan University

A nanopower switched-capacitor CMOS sub-bandgap voltage reference has been implemented using a Chartered 035-μm 3.3-V/5-V dual gate mixed-signal CMOS *** proposed circuit generates a precise sub-bandgap voltage of 1 *** temperature coefficient of the output voltage is 13.4 ppm/℃with the temperature varying from -20 to 80℃.The proposed circuit operates properly with the supply voltage down to 1.3 V,and consumes 150 nA at room *** line regulation is 0.27%/*** power supply rejection ratio at 100 Hz and 1 MHz is -39 dB and -51 dB,*** chip area is 0.2 mm2.

关键词： nanopower sub-bandgap switched-capacitor voltage reference

Sub-1V CMOS voltage reference Based on Weighted V_(gs)

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Journal of Semiconductors 2006年第5期27卷 774-777页

作者：张洵王鹏靳东明清华大学微电子学研究所北京100084

We propose a voltage reference based on the weighted difference between the gate-source voltages of an nMOS and a pMOS operating in their saturation regions. No diodes or parasitic bipolar transistors are used, The circuit is simulated and fabricated with SMIC 0.18μm mixed-signal technology,and our measurements demonstrate that its temperature coefficient is 44ppm/℃ and its PSRR is - 46dB, It works well when Vdd is above 650mV. The active area of the circuit is about 0.05mm^2.

关键词： voltage reference temperature coefficient power supply rejection ratio

A Novel CMOS voltage reference Based on Threshold voltage Difference Between p-Type and n-Type MOSFETs

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Journal of Semiconductors 2007年第10期28卷 1546-1550页

作者：孔明郭健民张科李文宏复旦大学专用集成电路与系统国家重点实验室上海201203

A novel MOS-only voltage reference is presented,which is based on the threshold voltage difference between p-type and n-type MOSFETs. Its precision is improved by the cancellation of the process variation. The reference has been successfully implemented in a Chartered 0.35μm CMOS process. The occupied chip area is 0. 022mm^2. Measurements indicate that without trimming, the average output voltage error is 6mV at room temperature compared with the simulation result. The temperature coefficient is 180ppm/℃ in the worst case in the temperature range of 0 to 100℃ ,and the line regulation is ± 1.1%. The reference is applied in an adaptive power MOSFET driver.

关键词： MOS-only voltage reference threshold voltage temperature coefficient line regulation

A embedded CMOS voltage reference IP core

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A embedded CMOS voltage reference IP core

A low drift curvature-compensated bandgap reference with trimming resistive circuit

2004 7th International Conference on Solid-State and Integrated Circuits Technology（ICSICT 2004）

作者： Zhangming Zhu~* and Yintang Yang Microelectronics Institute Xidian University Xi an 710071 China

＜正＞This paper presents an experimental case study of the embedded CMOS analog IP core for SOC *** on the research and analysis of embedded analog IP cores characteristic and design spec,the embedded voltage reference IP core is implemented by adopting high speed self bias amplifier and sub-threshold characteristic of *** core have the advantages of temperature compensation and width supply source voltage,and the output voltage of reference can be flexibly changed by adjusting resistor The IP core was implemented by TSMC 0.35 m,0.25 m and 0.18 m CMOS *** measured results show that the temperature coefficient less than 15ppm/K and the power current less than 5.2 ***,the design methodology of embedded CMOS analog IP core is summarized.

关键词： Embedded analog IP core SOC CMOS voltage reference

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Journal of Zhejiang University-Science C(Computers and Electronics) 2011年第8期12卷 698-706页

作者： Zhi-hua NING Le-nian HE Institute of Very Large Scale Integrated Circuits Zhejiang University Hangzhou 310027 China

A low temperature drift curvature-compensated complementary metal oxide semiconductor (CMOS) bandgap ref-erence is proposed.A dual-differential-pair amplifier was employed to add compensation with a high-order term of TlnT (T is the thermodynamic temperature) to the traditional 1st-order compensated *** reduce the offset of the amplifier and noise of the bandgap reference,input differential metal oxide semiconductor field-effect transistors (MOSFETs) of large size were used in the amplifier and to keep a low quiescent current,these MOSFETs all work in weak *** voltage reference's temperature curvature has been further corrected by trimming a switched resistor *** circuit delivers an output voltage of 3 V with a low dropout regulator (LDO).The chip was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC)'s 0.35-μm CMOS process,and the temperature coefficient (TC) was measured to be only 2.1×10 6/°C over the temperature range of 40-125 °C after *** power supply rejection (PSR) was 100 dB @ DC and the noise was 42 μV (rms) from 0.1 to 10 Hz.

关键词： voltage reference Bandgap Temperature compensation Low drift Resistive trimming

A 530 nA quiescent current low-dropout regulator with embedded reference for wake-up receivers

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Science China(Information Sciences) 2020年第12期63卷 281-283页

作者： Shaoquan GAO Hanjun JIANG Fule LI Zhihua WANG Institute of Microelectronics Tsinghua University

Dear editor,Low power transceivers are essential in the wireless personal area network (WPAN) applications [1].To reduce transceivers’ power in standby mode,wake-up receivers (WuR x’s) are now widely used in WPAN applications [2]. Those WuR x’s are always-on in the system and are usually powered by batteries. A compact low-dropout (LDO) voltage regulator with very small quiescent current is required to convert the battery voltage to the desired working voltage.

关键词： LDO low quiescent current voltage reference wake-up receiver adaptive biasing