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Short-channel effects on the static noise margin of 6T sram composed of 2D semiconductor MOSFETs

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Science China(Information Sciences) 2019年第6期62卷 98-105页

作者： Qian XIE Chen CHEN Mingjun LIU Shuang XIA Zheng WANG School of Electronic Science and Engineering University of Electronic Science and Technology of China

This paper investigates the influence of the short-channel effects（SCEs） on the static noise margin（SNM） of 6 T（6 transistors） sram composed of 2 D MOSFETs. An analytical all-region I-V model for short-channel complementary 2 D MOSFETs has been developed, and a simulation model has been built to calculate SNM with the consideration of SCEs and velocity saturation. The results show that there exists an optimal value of channel length(Lopt) where SNM reaches a maximum, and Lopt is approximately three times the scale length. In the region where L>Lopt, SNM increases slightly as L decreases because of velocity saturation, while in the region where L更多还原AbstractFilter('ChDivSummary', 'ChDivSummaryMore', 'ChDivSummaryReset');

关键词： 2D semiconductor model SNM SCEs sram

Low power and high write speed SEU tolerant sram data cell design

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Science China(Technological Sciences) 2015年第11期58卷 1983-1988页

作者： WANG Li ZHANG GuoHe ZENG YunLin SHAO ZhiBiao Department of Microelectronics Xi'an Jiaotong University

As feature size scales down, reliability issues like single event upset(SEU) have become serious for circuit and system designers, especially for those who work on memory and latch designs. In this paper, an improved SEU tolerant data cell design based on the Quatro-10 T cell is proposed. The introduced cell enhances the capability of SEU tolerance by weakening the key transistors in the feedback loop to block the effects of transient fault. Simulation results show that our proposed design achieves obvious higher resilience to SEU and better performance on speed and power dissipation at the expense of an increased area. The proposed cell is a fully SEU immune design with an amount of critical charge at least 7 times more than the Quatro-10 T cell and has the lowest Power Delay Product. It shows that our design is very suitable in high-performance circuit and system design.

关键词： single event upset sram low power high speed

Security strategy of powered-off sram for resisting physical attack to data remanence

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Journal of Semiconductors 2009年第9期30卷 102-106页

作者：余凯邹雪城余国义王伟旭 Department of Electronic Science and Technology Huazhong University of Science and Technology

This paper presents a security strategy for resisting a physical attack utilizing data remanence in powered- off static random access memory （sram）. Based on the mechanism of physical attack to data remanence, the strategy intends to erase data remanence in memory cells once the power supply is removed, which disturbs attackers trying to steal the right information. Novel on-chip secure circuits including secure power supply and erase transistor are integrated into conventional sram to realize erase operation. Implemented in 0.25μm Huahong-NEC CMOS technology, an sram exploiting the proposed security strategy shows the erase operation is accomplished within 0.2 μs and data remanence is successfully eliminated. Compared with conventional sram, the retentive time of data remanence is reduced by 82% while the operation power consumption only increases by 7%.

关键词： sram security strategy physical attack data remanence low-voltage low-power

A novel high reliability CMOS sram cell

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Journal of Semiconductors 2011年第7期32卷 131-135页

作者：谢成民王忠芳吴龙胜刘佑宝 Computer Research & Design Department Xi'an Microelectronic Technique Institutes

A novel 8T single-event-upset（SEU） hardened and high static noise margin（SNM） sram cell is proposed. By adding one transistor paralleled with each access transistor,the drive capability of pull-up PMOS is greater than that of the conventional cell and the read access transistors are weaker than that of the conventional *** the hold,read SNM and critical charge increase *** simulation results show that the critical charge is almost three times larger than that of the conventional 6T cell by appropriately sizing the pull-up *** hold and read SNM of the new cell increase by 72%and 141.7%,respectively,compared to the 6T design,but it has a 54%area overhead and read performance *** to these features,this novel cell suits high reliability applications,such as aerospace and military.

关键词： single-event-upset static noise margin critical charge sram

sram standby leakage decoupling analysis for different leakage reduction techniques

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Journal of Semiconductors 2013年第4期34卷 107-111页

作者：董庆林殷茵 State Key Laboratory of ASIC & System Fudan University

sram standby leakage reduction plays a pivotal role in minimizing the power consumption of ap- plication processors. Generally, four kinds of techniques are often utilized for sram standby leakage reduction： Vdd lowering （VDDL）, Vss rising （VSSR）, BL floating （BLF） and reversing body bias （RBB）. In this paper, we comprehensively analyze and compare the reduction effects of these techniques on different kinds of leakage. It is disclosed that the performance of these techniques depends on the leakage composition of the sram cell and temperature. This has been verified on a 65 nm sram test macro.

关键词： sram standby power leakage reduction

Azimuthal dependence of single-event and multiple-bit upsets in sram devices with anisotropic layout

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Nuclear Science and Techniques 2015年第5期26卷 69-75页

作者：张战刚刘杰侯明东孙友梅苏弘古松耿超姚会军罗捷段敬来莫丹习凯恩云飞 Institute of Modern Physics Chinese Academy of Sciences University of Chinese Academy of Sciences Science and Technology on Reliability Physics and Application of Electronic Component Laboratory China Electronic Product Reliability and Environmental Testing Research Institute

Experimental evidence is presented showing obvious azimuthal dependence of single event upsets(SEU) and multiple-bit upset(MBU) patterns in radiation hardened by design(RHBD) and MBU-sensitive static random access memories(srams), due to the anisotropic device layouts. Depending on the test devices, a discrepancy from 24.5% to 50% in the SEU cross sections of dual interlock cell(DICE) srams is shown between two perpendicular ion azimuths under the same tilt angle. Significant angular dependence of the SEU data in this kind of design is also observed, which does not fit the inverse-cosine law in the effective LET method. Ion trajectory-oriented MBU patterns are identified, which is also affected by the topological distribution of sensitive volumes. Due to that the sensitive volumes are periodically isolated by the BL/BLB contacts along the Y-axis direction, double-bit upsets along the X-axis become the predominant configuration under normal *** triple-bit upset and quadruple-bit upset patterns are the same under different ion azimuths(Lshaped and square-shaped configurations, respectively). Those results suggest that traditional RPP/IRPP model should be promoted to consider the azimuthal and angular dependence of single event effects in certain *** earth-based evaluation of SEE sensitivity, worst case beam direction, i.e., the worst case response, should be revealed to avoid underestimation of the on-orbit error rate.

关键词： sram 各向异性方位角单事件翻转静态随机存取存储器器件设计模式

A novel layout for single event upset mitigation in advanced CMOS sram cells

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Science China(Technological Sciences) 2013年第1期56卷 143-147页

作者： QIN JunRui LI DaWei CHEN ShuMing School of Computer Science National University of Defense Technology

A novel layout has been proposed to reduce the single event upset(SEU) vulnerability of sram *** 3-D technology computer-aided design(TCAD) simulation analyses show that the proposed layout can recover the upset-state much easier than conventional layout for larger space of PMOS *** the angle incidence,the proposed layout is immune from ion hit in two plans,and is more robust against SEU in other two plans than the conventional *** ability of anti-SEU is enhanced by at least 33% while the area cost reduced by 47%.Consequently,the layout strategy proposed can gain both reliability and area cost benefit simultaneously.

关键词： single event upset layout technique sram radiation hardening by design

Predictive approach of SEU occurrence induced by neutron in sram and EEPROM

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Nuclear Science and Techniques 2015年第5期26卷 83-87页

作者：金晓明杨善潮李达张文首王晨辉李瑞宾王桂珍白小燕齐超刘岩 State Key Laboratory of Intense Pulsed Radiation Simulation and Effect Northwest Institute of Nuclear Technology

A simulation approach is developed to obtain the linear energy transfer(LET) spectrum of all secondary ions and predict single event upset(SEU) occurrence induced by neutron in memory devices. Neutron reaction channels, secondary ion species and energy ranges, and LET calculation method are introduced respectively. Experimental results of neutron induced SEU effects on static random access memory(sram) and programmable read only memory(EEPROM) are presented to confirm the validity of the simulation results.

关键词： EEPROM 中子诱发 sram SEU 预测静态随机存取存储器可编程只读存储器离子种类

Simulation and research on a 4T-cell based duplication redundancy sram for SEU radiation hardening

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Journal of Semiconductors 2015年第11期36卷 34-38页

作者：洪新红潘立阳张文帝纪冬梅伍冬沈忱许军 Institute of Microelectronics Tsinghua University Cogenda Co Ltd

A novel 4T-cell based duplication redundancy sram is proposed for SEU radiation hardening applications. The memory cell is designed with a 65-nm low leakage process; the operation principle and the SEU radiation hardening mechanism are discussed in detail. The SEE characteristics and failure mechanism are also studied with a 3-D device simulator. The results show that the proposed sram structure exhibits high SEU hardening performance with a small cell size.

关键词： sram SEE SEU radiation hardening 3-D simulation