Security strategy of powered-off SRAM for resisting physical attack to data remanence

作     者：余凯 邹雪城 余国义 王伟旭 

作者机构：Department of Electronic Science and TechnologyHuazhong University of Science and Technology 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2009年第30卷第9期

页      面：102-106页

核心收录：

学科分类：030207[法学-国际关系] 03[法学] 0302[法学-政治学] 08[工学] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Project supported by the National Natural Science Foundation of China (No.60776027) 

主　　题：SRAM security strategy physical attack data remanence low-voltage low-power 

摘      要：This paper presents a security strategy for resisting a physical attack utilizing data remanence in powered- off static random access memory （SRAM）. Based on the mechanism of physical attack to data remanence, the strategy intends to erase data remanence in memory cells once the power supply is removed, which disturbs attackers trying to steal the right information. Novel on-chip secure circuits including secure power supply and erase transistor are integrated into conventional SRAM to realize erase operation. Implemented in 0.25μm Huahong-NEC CMOS technology, an SRAM exploiting the proposed security strategy shows the erase operation is accomplished within 0.2 μs and data remanence is successfully eliminated. Compared with conventional SRAM, the retentive time of data remanence is reduced by 82% while the operation power consumption only increases by 7%.