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OPTIMIZED reversible ARITHMETIC logic UNITS

Journal of Electronics(China) 2014年第5期31卷 394-405页

作者： Payman Moallem Maryam Ehsanpour Ali Bolhasani Mehrdad Montazeri Department of Electrical Engineering University of Isfahan Department of Computer Falavarjan Branch Islamic Azad University Department of Computer Arak Branch Islamic Azad University Department of Computer Faculty of Engineering Polytechnic University of Turin

Arithmetic logic Unit(ALU) as one of the main parts of any computing hardware plays an important role in digital computers. In quantum computers which can be realized by reversible logics and circuits, reversible ALUs should be designed. In this paper, we proposed three different designs for reversible 1-bit ALUs using our proposed 3×3 and 4×4 reversible gates called MEB3 and MEB4(Moallem Ehsanpour Bolhasani) gates, respectively. The first proposed reversible ALU consists of six logical operations. The second proposed ALU consists of eight operations, two arithmetic, and six logical operations. And finally, the third proposed ALU consists of sixteen operations, four arithmetic operations, and twelve logical operations. Our proposed ALUs can be used to construct efficient quantum computers in nanotechnology, because the proposed designs are better than the existing designs in terms of quantum cost, constant input, reversible gates used, hardware complexity, and functions generated.

关键词： reversible Arithmetic logic Unit(ALU) Full Adder(FA) Control unit reversible logic gates

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Design and Implementation of Efficient reversible Arithmetic and logic Unit

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Circuits and Systems 2016年第6期7卷 630-642页

作者： Subramanian Saravanan Ila Vennila Sudha Mohanram Department of EEE P. S. G. College of Technology Coimbatore India Sri Eshwar College of Engineering Kondampatty Coimbatore India

In computing architecture, ALU plays a major role. Many promising applications are possible with ATMEGA microcontroller. ALU is a part of these microcontrollers. The performance of these microcontrollers can be improved by applying reversible logic and Vedic Mathematics. In this paper, an efficient reversible Arithmetic and logic Unit with reversible Vedic Multiplier is proposed and the simulation results show its effectiveness in reducing quantum cost, number of gates, and the total number of logical calculations.

关键词： reversible logic gates reversible logic Circuits reversible Multiplier Circuits Vedic Multiplier ALU

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Design and Implementation of an Efficient reversible Comparator Using TR Gate

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Circuits and Systems 2016年第9期7卷 2578-2592页

作者： Subramanian Saravanan Ila Vennila Sudha Mohanram Department of EEE P. S. G. College of Technology Coimbatore India Sri Eshwar College of Engineering Kondampatty India

reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computing, etc. In industrial automation, comparators play an important role in segregating faulty patterns from good ones. In previous works, these comparators have been implemented with more number of reversible gates and computational complexity. All these comparators use propagation technique to compare the data. This will reduce the efficiency of the comparators. To overcome the problem, this paper proposes an efficient comparator using (Thapliyal Ranganathan) TR gate utilizing full subtraction and half subtraction algorithm which will improve the computation efficiency. The comparator design using half subtraction algorithm shows an improvement in terms of quantum cost. The comparator design using full subtraction algorithm shows effectiveness in reducing number of reversible gates required and garbage output.

关键词： reversible logic gates reversible logic Circuits (Very Large Scale Integration) VLSI Design

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