Design and Implementation of Efficient Reversible Arithmetic and Logic Unit

作     者：Subramanian Saravanan Ila Vennila Sudha Mohanram Subramanian Saravanan;Ila Vennila;Sudha Mohanram

作者机构：Department of EEE P. S. G. College of Technology Coimbatore India Sri Eshwar College of Engineering Kondampatty Coimbatore India 

出 版 物：《Circuits and Systems》 (电路与系统（英文）)

年 卷 期：2016年第7卷第6期

页      面：630-642页

学科分类：0401[教育学-教育学] 04[教育学] 

主　　题：Reversible Logic Gates Reversible Logic Circuits Reversible Multiplier Circuits Vedic Multiplier ALU 

摘      要：In computing architecture, ALU plays a major role. Many promising applications are possible with ATMEGA microcontroller. ALU is a part of these microcontrollers. The performance of these microcontrollers can be improved by applying Reversible Logic and Vedic Mathematics. In this paper, an efficient reversible Arithmetic and Logic Unit with reversible Vedic Multiplier is proposed and the simulation results show its effectiveness in reducing quantum cost, number of gates, and the total number of logical calculations.