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Fast Weighted Bit Flipping Algorithm for Higher-Speed Decoding of Low-Density Parity-Check Codes

China Communications 2013年第9期10卷 114-119页

作者：马克祥李勇朝张海林 National Key Laboratory on ISN Xidian University

Because of the speed limitation of the conventional bit-selection strategy in the exi- sting weighted bit flipping algorithms, a high- speed Low-Density Parity-Check （LDPC） dec- oder cannot be realised. To solve this problem, we propose a fast weighted bit flipping algo- rithm. Specifically, based on the identically dis- tributed error bits, a parallel bit-selection met- hod is proposed to reduce the selection delay of the flipped bits. The delay analysis demon- strates that, the decoding speed of LDPC codes can be significantly improved by the proposed algorithm. Furthermore, simulation results ver- ify the validity of the proposed algorithm.

关键词： LDPC weighted bit flipping par-tially parallel pipelined

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High-Throughput and Area-Efficient FPGA Implementations of Data Encryption Standard (DES)

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Circuits and Systems 2014年第3期5卷 45-56页

作者： Raed Bani-Hani Salah Harb Khaldoon Mhaidat Eyad Taqieddin Department of Computer Engineering Jordan University for Science and Technology Irbid Jordan Department of Network Engineering and Security Jordan University for Science and Technology Irbid Jordan

One of the most popular standards for protecting confidential information is the Data Encryption Standard (DES). Although it has been replaced by the Advanced Encryption Standard (AES), it is still widely used in Automatic Teller Machines (ATM’s), smartcards, and mobile phone SIM cards. In this paper, we present area-efficient and high-throughput FPGA implementations of the DES which are developed using the Xilinx FPGA ISE design suite. In fact, we propose modifications on the fastest DES design reported in the literature and achieve 1.1 times higher speed. Also, we introduce an 8-stage pipelined design that needs only 0.75 times the registers and consumes 0.65 times the power of a similar 16-stages pipelined design. High-speed design and synthesis optimization techniques including pipelining, register retiming, and logic replication are used. Post- layout synthesis results show that the proposed implementations achieve high throughput-to-area ratio. To make a fair comparison, the proposed designs were synthesized using matching FPGA devices as being used by other implementations reported in the literature.

关键词： DES FPGA pipelined Iterative Security Efficiency Encryption

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A Fast FPGA Implementation for Triple DES Encryption Scheme

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Circuits and Systems 2017年第9期8卷 237-246页

作者： Edni Del Rosal Sanjeev Kumar IEEE Network Security Research Lab Department of Electrical/Computer Engineering The University of Texas Rio Grande Valley Edinburg USA

In cryptography, the Triple DES (3DES, TDES or officially TDEA) is a symmetric-key block cipher which applies the Data Encryption Standard (DES) cipher algorithm three times to each data block. Electronic payment systems are known to use the TDES scheme for the encryption/decryption of data, and hence faster implementations are of great significance. Field Programmable Gate Arrays (FPGAs) offer a new solution for optimizing the performance of applications meanwhile the Triple Data Encryption Standard (TDES) offers a mean to secure information. In this paper we present a pipelined implementation in VHDL, in Electronic Code Book (EBC) mode, of this commonly used cryptography scheme with aim to improve performance. We achieve a 48-stage pipeline depth by implementing a TDES key buffer and right rotations in the DES decryption key scheduler. Using the Altera Cyclone II FPGA as our platform, we design and verify the implementation with the EDA tools provided by Altera. We gather cost and throughput information from the synthesis and timing results and compare the performance of our design to common implementations presented in other literatures. Our design achieves a throughput of 3.2 Gbps with a 50 MHz clock;a performance increase of up to 16 times.

关键词： Data Encryption Standard Triple DES DES TDES 3DES Non-pipelined pipelined Cyclone II FPGA VHDL

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