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An efficient wear-leveling-aware multi-grained allocator for persistent memory file systems

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Frontiers of Information Technology & Electronic Engineering 2023年第5期24卷 688-702页

作者： Zhiwang YU Runyu ZHANG Chaoshu YANG Shun NIE Duo LIU State Key Laboratory of Public Big Data College of Computer Science and TechnologyGuizhou UniversityGuiyang 550000China College of Computer Science Chongqing UniversityChongqing 404100China

persistent memory(PM)file systems have been developed to achieve high performance by exploiting the advanced features of PMs,including nonvolatility,byte addressability,and dynamic random access memory(DRAM)like ***,these PMs suffer from limited write *** space management strategies of PM file systems can induce a severely unbalanced wear problem,which can damage the underlying PMs *** this paper,we propose a Wear-leveling-aware Multi-grained Allocator,called WMAlloc,to achieve the wear leveling of PMs while improving the performance of file *** adopts multiple min-heaps to manage the unused space of *** heap represents an allocation ***,WMAlloc allocates less-worn blocks from the corresponding min-heap for allocation ***,to avoid recursive split and inefficient heap locations in WMAlloc,we further propose a bitmap-based multi-heap tree(BMT)to enhance WMAlloc,namely,*** implement WMAlloc and WMAlloc-BMT in the Linux kernel based on NOVA,a typical PM file *** results show that,compared with the original NOVA and dynamic wear-aware range management(DWARM),which is the state-of-the-art wear-leveling-aware allocator of PM file systems,WMAlloc can,respectively,achieve 4.11×and 1.81×maximum write number reduction and 1.02×and 1.64×performance with four workloads on ***,WMAlloc-BMT outperforms WMAlloc with 1.08×performance and achieves 1.17×maximum write number reduction with four workloads on average.

关键词： File system persistent memory Wear-leveling Multi-grained allocator

A survey of operating system support for persistent memory

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Frontiers of Computer Science 2021年第4期15卷 29-48页

作者： Miao CAI Hao HUANG Department of Computer Science and Technology Nanjing UniversityNanjing 210023China

Emerging persistent memory technologies,like PCM and 3D XPoint,offer numerous advantages,such as higher density,larger capacity,and better energy efficiency,compared with the ***,they also have some drawbacks,e.g.,slower access speed,limited write endurance,and unbalanced read/write *** memory technologies provide both great opportunities and challenges for operating *** a result,a large number of solutions have been *** the increasing number and complexity of problems and approaches,we believe this is the right moment to investigate and analyze these works *** this end,we perform a comprehensive and in-depth study on operating system support for persistent memory within three ***,we present an overview of how to build the operating system on persistent memory from three perspectives:system abstraction,crash consistency,and system ***,we classify the existing research works into three categories:storage stack,memory manager,and OS-bypassing *** each category,we summarize the major research topics and discuss these topics ***,we present the challenges and opportunities in each topic,describe the contributions and limitations of proposed approaches,and compare these solutions in different ***,we also envision the future operating system based on this study.

关键词： persistent memory operating system survey

Revisiting persistent Indexing Structures on Intel Optane DCpersistent memory

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Journal of Computer Science & Technology 2021年第1期36卷 140-157页

作者： Heng Bu Ming-Kai Dong Ji-Fei Yi Bin-Yu Zang Hai-Bo Chen Institute of Parallel and Distributed Systems Shanghai Jiao Tong UniversityShanghai 200240China

persistent indexing structures are proposed in response to emerging non-volatile memory(NVM)to provide high performance yet durable ***,due to the lack of real NVM hardware,many prior persistent indexing structures were evaluated via emulation,which varies a lot across different setups and differs from the real ***,Intel has released its Optane DC persistent memory Module(PMM),which is the first production-ready *** this paper,we revisit popular persistent indexing structures on PMM and conduct comprehensive evaluations to study the performance differences among persistent indexing structures,including persistent hash tables and persistent *** to the evaluation results,we find that Cacheline-Conscious Extendible Hashing(CCEH)achieves the best performance among all evaluated persistent hash tables,and Failure-Atomic ShifT B+-Tree(FAST)and Write Optimal Radix Tree(WORT)perform better than other ***,we find that the insertion performance of hash tables is heavily influenced by data locality,while the insertion latency of trees is dominated by the flush *** also uncover that no existing emulation methods accurately simulate PMM for all the studied data ***,we provide three suggestions on how to fully utilize PMM for better performance,including using clflushopt/clwb with sfence instead of clflush,flushing continuous data in a batch,and avoiding data access immediately after it is flushed to PMM.

关键词： persistent memory data structure performance Intel Optane DC persistent memory module(PMM)

Dalea:A persistent Multi-Level Extendible Hashing with Improved Tail Performance

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Journal of Computer Science & Technology 2023年第5期38卷 1051-1073页

作者：熊子威蒋德钧熊劲 Ren Ren Center for Advanced Computer Systems Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 101408China Huawei Technology Co. Ltd.Shanghai 201206China

persistent memory(PM)promises byte-addressability,large capacity,and *** memory systems,such as key-value stores and in-memory databases,benefit from such features of *** to the great popularity of hash-ing index in main memory systems,a number of research efforts are made to provide high average performance persistent ***,suboptimal tail performance in terms of tail throughput and tail latency is still observed for existing persistent *** this paper,we analyze major sources of suboptimal tail performance from key design issues of persis-tent *** identify the global hash structure and concurrency control as remaining explorable design spaces for im-proving tail *** propose Directory-sharing Multi-level Extendible Hashing(Dalea)for *** designs an-cestor link-based extendible hashing as well as fine-grained transient lock to address the two main sources(rehashing and locking)affecting tail *** evaluation results show that,compared with state-of-the-art persistent hashing Dash,Dalea achieves increased tail throughput by 4.1x and reduced tail latency by ***,in order to provide de-sign guidelines for improving tail performance,we adopt Dalea as a testbed to identify different impacts of four factors on tail performance,including fine-grained rehashing,transient locking,memory pre-allocation,and fingerprinting.

关键词： persistent memory persistent hashing indexing structure

Reducing Synchronization Cost for Single-Level Store in Mobile Systems

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Journal of Computer Science & Technology 2016年第4期31卷 836-848页

作者： Yuan-Chao Xu Hu Wan Ke-Ni Qiu Tao Li Wei-Gong Zhang College of Information Engineering Capital Normal University Beijing 100048 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Department of Electrical and Computer Engineering University of Florida Gainesville FL 32611 U.S.A.

Emerging byte-addressable non-volatile memory technologies, such as phase change memory （PCM） and spin- transfer torque RAM （STT-RAM）, offer both the byte-addressability of memory and the durability of storage, thus making it feasible to build single-level store systems. To ensure the consistency of persistent data structures in the presence of power failures or system crashes, it requires flushing cache lines to persistent memory frequently, thus incurring non-trivial synchronization overhead. To mitigate this issue, we propose two techniques. First, we use non-volatile STT-RAM as scratchpad memory on chip to store recovery information, thereby eliminating synchronization cost in the logging phase due to the avoidance of off-chip logging operations. Second, we present an adaptive synchronization policy based on caching modes in terms of data access patterns, thereby eliminating unnecessary synchronization cost in the checkpoint phase. Evaluation results indicate that the two techniques improve the overall performance from 2.15x to 2.39x compared with conventional transactional persistent memory.

关键词： crash consistency synchronization cost persistent memory power failure mobile system

A Survey of Non-Volatile Main memory Technologies:State-of-the-Arts,Practices,and Future Directions

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Journal of Computer Science & Technology 2021年第1期36卷 4-32页

作者： Hai-Kun Liu Di Chen Hai Jin Xiao-Fei Liao Binsheng He Kan Hu Yu Zhang National Engineering Research Center for Big Data Technology and System Huazhong University of Science and TechnologyWuhan 430074China Services Computing Technology and System Laboratory Huazhong University of Science and Technology Wuhan 430074China Cluster and Grid Computing Laboratory Huazhong University of Science and TechnologyWuhan 430074China School of Computing Science and Technology Huazhong University of Science and TechnologyWuhan 430074China School of Computing National University of SingaporeSingapore 117418Singapore

Non-Volatile Main Memories (NVMMs) have recently emerged as a promising technology for future memory systems. Generally, NVMMs have many desirable properties such as high density, byte-addressability, non-volatility, low cost, and energy efficiency, at the expense of high write latency, high write power consumption, and limited write endurance. NVMMs have become a competitive alternative of Dynamic Random Access memory (DRAM), and will fundamentally change the landscape of memory systems. They bring many research opportunities as well as challenges on system architectural designs, memory management in operating systems (OSes), and programming models for hybrid memory systems. In this article, we revisit the landscape of emerging NVMM technologies, and then survey the state-of-the-art studies of NVMM technologies. We classify those studies with a taxonomy according to different dimensions such as memory architectures, data persistence, performance improvement, energy saving, and wear leveling. Second, to demonstrate the best practices in building NVMM systems, we introduce our recent work of hybrid memory system designs from the dimensions of architectures, systems, and applications. At last, we present our vision of future research directions of NVMMs and shed some light on design challenges and opportunities.

关键词： non-volatile memory persistent memory hybrid memory systems memory hierarchy

RCache: A Read-Intensive Workload-Aware Page Cache for NVM Filesystem

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ZTE Communications 2023年第1期21卷 89-94页

作者： TU Yaofeng ZHU Bohong YANG Hongzhang HAN Yinjun SHU Jiwu State Key Laboratory of Mobile Network and Mobile Multimedia Technology Shenzhen 518055China ZTE Corporation Shenzhen 518057China Tsinghua University Beijing 100084China

Byte-addressable non-volatile memory(NVM),as a new participant in the storage hierarchy,gives extremely high performance in storage,which forces changes to be made on current filesystem *** cache,once a significant mechanism filling the performance gap between Dynamic Random Access memory(DRAM)and block devices,is now a liability that heavily hinders the writing performance of NVM *** state-of-the-art NVM filesystems leverage the direct access(DAX)technology to bypass the page cache ***,the DRAM still provides higher bandwidth than NVM,which prevents skewed read workloads from benefiting from a higher bandwidth of the DRAM and leads to sub-optimal performance for the *** this paper,we propose RCache,a readintensive workload-aware page cache for NVM *** from traditional caching mechanisms where all reads go through DRAM,RCache uses a tiered page cache design,including assigning DRAM and NVM to hot and cold data separately,and reading data from both *** avoid copying data to DRAM in a critical path,RCache migrates data from NVM to DRAM in a background ***,RCache manages data in DRAM in a lock-free manner for better latency and *** on Intel Optane Data Center(DC)persistent memory Modules show that,compared with NOVA,RCache achieves 3 times higher bandwidth for read-intensive workloads and introduces little performance loss for write operations.

关键词： storage system file system persistent memory

A Survey of System Software Techniques for Emerging NVMs

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ZTE Communications 2017年第1期15卷 35-42页

作者： BAI Tongxin DONG Zhenjiang CAI Manyi FAN Xiaopeng XU Chengzhong LIU Lixia Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences Shenzhen 518055 China ZTE Corporation Nanjing 210012 China

The challenges of power consumption and memory capacity of computers have driven rapid development on non-volatile memories(NVM).NVMs are generally faster than traditional secondary storage devices,write persistently and many offer byte addressing *** these appealing features,NVMs are difficult to manage and program,which makes it hard to use them as a drop-in replacement for dynamic random-access memory(DRAM).Instead,a majority of modern systems use NVMs through the IO and the file system *** NVMs under these interfaces poses challenges on how to exploit the new hardware’s performance potential in the existing system software *** this article,we survey the key technical issues arisen in this area and introduce several recently developed systems each of which offers novel solutions around these issues.

关键词： non-volatile memory persistent memory file system IO system