Reducing Synchronization Cost for Single-Level Store in Mobile Systems
Reducing Synchronization Cost for Single-Level Store in Mobile Systems作者机构：College of Information Engineering Capital Normal University Beijing 100048 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Department of Electrical and Computer Engineering University of Florida Gainesville FL 32611 U.S.A.
出 版 物：《Journal of Computer Science & Technology》 (计算机科学技术学报（英文版）)
年 卷 期：2016年第31卷第4期
页 面：836-848页
核心收录：
学科分类：11[军事学] 1105[军事学-军队指挥学] 0839[工学-网络空间安全] 08[工学] 110505[军事学-密码学] 081201[工学-计算机系统结构] 110503[军事学-军事通信学] 0812[工学-计算机科学与技术（可授工学、理学学位）]
基 金：This work was supported by the National Natural Science Foundation of China under Grant Nos. 61502321 61472260 and 61402302 the Beijing Natural Science Foundation under Grant No. 4143060 the Overseas Visiting Scholar Program of Beijing under Grant No. 067135300100 the State Key Laboratory of Computer Architecture of China under Grant No. CARCH201503 and the Beijing Innovative Teams and Teacher Career Development Program under Grant No. IDHT20150507
主 题：crash consistency synchronization cost persistent memory power failure mobile system
摘 要：Emerging byte-addressable non-volatile memory technologies, such as phase change memory （PCM） and spin- transfer torque RAM （STT-RAM）, offer both the byte-addressability of memory and the durability of storage, thus making it feasible to build single-level store systems. To ensure the consistency of persistent data structures in the presence of power failures or system crashes, it requires flushing cache lines to persistent memory frequently, thus incurring non-trivial synchronization overhead. To mitigate this issue, we propose two techniques. First, we use non-volatile STT-RAM as scratchpad memory on chip to store recovery information, thereby eliminating synchronization cost in the logging phase due to the avoidance of off-chip logging operations. Second, we present an adaptive synchronization policy based on caching modes in terms of data access patterns, thereby eliminating unnecessary synchronization cost in the checkpoint phase. Evaluation results indicate that the two techniques improve the overall performance from 2.15x to 2.39x compared with conventional transactional persistent memory.
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