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General Purpose Framework Designing for Network Security Test Devices Based on Multi-core processor

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General Purpose Framework Designing for Network Security Tes...

Schedule refinement for homogeneous Multi-core processors in the presence of manufacturing-caused heterogeneity

2012年计算机应用与系统建模国际会议

作者： Shi Guozhen Li Fenghua Li Li Shi Hanzhang Department of Electronic Engineering Beijing Electronic Science and Technology Institute School of Computer Science and Technology Xidian University

In view of the present situation that network security equipments are deployed widely but their security strategies are not open to public, this paper analyzed currently used general test method for network security equipments, proposed a general purpose framework for test devices based on Multi-core processor and performed a proof implementation on Tile64 processor platform. The general purpose framework includes three parts: the General network processing module and special communication protocols, master controlled dispatching module and special equipment test module. In the general purpose framework, the special test module can be loaded according to current requirement. In this basis, several problems that often exist in network security equipments test can be solved, such as security strategy leaking, batch processing for test devices and synchronous online tests for equipments of different types.

关键词： Testing devices Network security General purpose framework Multi-core processor

来源： cnki会议评论

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Frontiers of Information Technology & Electronic Engineering 2015年第12期16卷 1018-1033页

作者： Zhi-xiang CHEN Zhao-lin LI Shan CAO Fang WANG Jie ZHOU Department of Automation Tsinghua University Institute of Microelectronics Tsinghua University Research Institute of Information Technology Tsinghua University Tsinghua National Laboratory for Information Science and Technology Tsinghua University The School of Information and Electronics Beijing Institute of Technology

multi-core homogeneous processors have been widely used to deal with computation-intensive embedded applications. However, with the continuous down scaling of CMOS technology, within-die variations in the manufacturing process lead to a significant spread in the operating speeds of cores within homogeneous Multi-core processors. Task scheduling approaches, which do not consider such heterogeneity caused by within-die variations,can lead to an overly pessimistic result in terms of performance. To realize an optimal performance according to the actual maximum clock frequencies at which cores can run, we present a heterogeneity-aware schedule refining(HASR) scheme by fully exploiting the heterogeneities of homogeneous Multi-core processors in embedded domains.We analyze and show how the actual maximum frequencies of cores are used to guide the scheduling. In the scheme,representative chip operating points are selected and the corresponding optimal schedules are generated as candidate schedules. During the booting of each chip, according to the actual maximum clock frequencies of cores, one of the candidate schedules is bound to the chip to maximize the performance. A set of applications are designed to evaluate the proposed scheme. Experimental results show that the proposed scheme can improve the performance by an average value of 22.2%, compared with the baseline schedule based on the worst case timing analysis. Compared with the conventional task scheduling approach based on the actual maximum clock frequencies, the proposed scheme also improves the performance by up to 12%.

关键词： Schedule refining Multi-core processor Heterogeneity Representative chip operating point

维普期刊数据库

Shared Cache Based on Content Addressable Memory in a multi-core Architecture

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Computers, Materials & Continua 2023年第3期74卷 4951-4963页

作者： Allam Abumwais Mahmoud Obaid Computer Systems Engineering Arab American UniversityJenin240Palestine

Modern shared-memory Multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to access the shared cache simultaneously.The main problem in improving memory performance is the shared cache architecture and cache replacement.This paper documents the implementation of a Dual-Port Content Addressable Memory(DPCAM)and a modified Near-Far Access Replacement Algorithm(NFRA),which was previously proposed as a shared L2 cache layer in a Multi-core processor.Standard Performance Evaluation Corporation(SPEC)Central Processing Unit(CPU)2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache layer.Results show improved performance of the multicore processor’s DPCAM and NFRA algorithms,corresponding to a higher number of concurrent accesses to shared memory.The new architecture significantly increases system throughput and records performance improvements of up to 8.7%on various types of SPEC 2006 benchmarks.The miss rate is also improved by about 13%,with some exceptions in the sphinx3 and bzip2 benchmarks.These results could open a new window for solving the long-standing problems with shared cache in Multi-core processors.

关键词： Multi-core processor shared cache content addressable memory dual port CAM replacement algorithm benchmark program

System Architecture of Godson-3 Multi-core processors

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Journal of Computer Science & Technology 2010年第2期25卷 181-191页

作者：高翔陈云霁王焕东唐丹胡伟武 Institute of Computing Technology Chinese Academy of Sciences Graduate University of Chinese Academy of Sciences

Godson-3 is the latest generation of Godson microprocessor family. It takes a scalable multi-core architecture with hardware support for accelerating applications including X86 emulation and signal processing. This paper introduces the system architecture of Godson-3 from various aspects including system scalability, organization of memory hierarchy, network-on-chip, inter-chip connection and I/O subsystem.

关键词： Multi-core processor scalable interconnection cache coherent non-uniform memory access/non-uniform cache access （CC-NUMA/NUCA） MESH crossbar cache coherence reliability availability and serviceability （RAS）

维普期刊数据库

The Design and Implementation of a Distributed Data Acquisition、Monitoring & Processing System (DDAMAP)

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软件工程 2011年第Z1期 123-127页

作者： Guoshun Zhou, Hua Shen, HuiQi Yan (Neusoft Institute of Information , Dalian Liaoning 116023)

This report presents the design and implementation of a Distributed Data Acquisition、 Monitoring and Processing System (DDAMAP)。It is assumed that operations of a factory are organized into two-levels: client machines at plant-level collect real-time raw data from sensors and measurement instrumentations and transfer them to a central processor over the Ethernets, and the central processor handles tasks of real-time data processing and monitoring. This system utilizes the computation power of Intel T2300 dual-core processor and parallel computations supported by multi-threading techniques. Our experiments show that these techniques can significantly improve the system performance and are viable solutions to real-time high-speed data processing.

关键词： Data acquisition rawdata Multi-core processor multi-thread programming distributed system parallel computation embedded systems.