Schedule refinement for homogeneous multi-core processors in the presence of manufacturing-caused heterogeneity

作     者：Zhi-xiang CHEN Zhao-lin LI Shan CAO Fang WANG Jie ZHOU 

作者机构：Department of AutomationTsinghua University Institute of MicroelectronicsTsinghua University Research Institute of Information TechnologyTsinghua University Tsinghua National Laboratory for Information Science and TechnologyTsinghua University The School of Information and ElectronicsBeijing Institute of Technology 

出 版 物：《Frontiers of Information Technology & Electronic Engineering》 (信息与电子工程前沿（英文版）)

年 卷 期：2015年第16卷第12期

页      面：1018-1033页

核心收录：

学科分类：0810[工学-信息与通信工程] 0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0839[工学-网络空间安全] 0835[工学-软件工程] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Project supported by the National Natural Science Foundation of China(Nos.61225008 61373074 and 61373090) the National Basic Research Program(973)of China(No.2014CB349304) the Specialized Research Fund for the Doctoral Program of Higher Education,the Ministry of Education of China(No.20120002110033) the Tsinghua University Initiative Scientific Research Program 

主　　题：Schedule refining Multi-core processor Heterogeneity Representative chip operating point 

摘      要：Multi-core homogeneous processors have been widely used to deal with computation-intensive embedded applications. However, with the continuous down scaling of CMOS technology, within-die variations in the manufacturing process lead to a significant spread in the operating speeds of cores within homogeneous multi-core processors. Task scheduling approaches, which do not consider such heterogeneity caused by within-die variations,can lead to an overly pessimistic result in terms of performance. To realize an optimal performance according to the actual maximum clock frequencies at which cores can run, we present a heterogeneity-aware schedule refining(HASR) scheme by fully exploiting the heterogeneities of homogeneous multi-core processors in embedded domains.We analyze and show how the actual maximum frequencies of cores are used to guide the scheduling. In the scheme,representative chip operating points are selected and the corresponding optimal schedules are generated as candidate schedules. During the booting of each chip, according to the actual maximum clock frequencies of cores, one of the candidate schedules is bound to the chip to maximize the performance. A set of applications are designed to evaluate the proposed scheme. Experimental results show that the proposed scheme can improve the performance by an average value of 22.2%, compared with the baseline schedule based on the worst case timing analysis. Compared with the conventional task scheduling approach based on the actual maximum clock frequencies, the proposed scheme also improves the performance by up to 12%.