检索结果-南通市图书馆

Inkjet printing technology for increasing the I/O density of 3D TSV interposers

在线全文

学校读者我要写书评

暂无评论

Microsystems & Nanoengineering 2017年第1期3卷 349-357页

作者： Behnam Khorramdel Jessica Liljeholm Mika-Matti Laurila Toni Lammi Gustaf Mårtensson Thorbjörn Ebefors Frank Niklaus Matti Mäntysalo Department of Electronics and Communications Engineering Tampere University of TechnologyKorkeakoulunkatu 3Tampere 33720Finland Silex Microsystems AB Bruttovägen 1Järfälla/Stockholm SE-17526Sweden Micro and Nanosystem KTH Royal Institute of TechnologyOsquldas väg 1010044 StockholmSweden EMSL Chalmers University of TechnologyKemivägen 941296 GöteborgSweden Mycronic AB Nytorpsvägen 918303 TäbySweden

interposers with through-silicon vias(TSVs)play a key role in the three-dimensional integration and packaging of integrated circuits and microelectromechanical *** the current practice of fabricating interposers,solder balls are placed next to the vias;however,this approach requires a large foot print for the input/output(I/O)***,in this study,we investigate the possibility of placing the solder balls directly on top of the vias,thereby enabling a smaller pitch between the solder balls and an increased density of the I/O *** reach this goal,inkjet printing(that is,piezo and super inkjet)was used to successfully fill and planarize hollow metal TSVs with a dielectric *** under bump metallization(UBM)pads were also successfully printed with inkjet technology on top of the polymer-filled vias,using either Ag or Au *** reliability of the TSV interposers was investigated by a temperature cycling stress test(−40℃ to+125℃).The stress test showed no impact on DC resistance of the TSVs;however,shrinkage and delamination of the polymer was observed,along with some micro-cracks in the UBM *** proof of concept,SnAgCu-based solder balls were jetted on the UBM pads.

关键词： heterogeneous three-dimensional(3D)integration inkjet printing interposer microelectromechanical system(MEMS) reliability super inkjet(SIJ) through silicon via(TSV)

TXV Technology:The cornerstone of 3D system-in-packaging

维普期刊数据库评论

在线全文

维普期刊数据库

学校读者我要写书评

暂无评论

Science China(Technological Sciences) 2022年第9期65卷 2031-2050页

作者： ZHAO HeRan CHEN MingXiang PENG Yang WANG Qing KANG Min CAO LiHua School of Mechanical Science and Engineering Huazhong University of Science and TechnologyWuhan 430074China The 47th Institute of China Electronics Technology Group Corporation Shenyang 110000China State Key Laboratory of Digital Manufacturing Equipment and Technology Huazhong University of Science and TechnologyWuhan 430074China School of Aerospace Engineering Huazhong University of Science and TechnologyWuhan 430074China Institute of Metal Research Chinese Academy of SciencesShenyang 110016China Shenyang National Laboratory for Materials Science Shenyang 110016China

System-in-packaging(Si P) can realize the integration and miniaturization of electronic devices and it is significant to continue Moore’s ***-X-via(TXV) technology is the cornerstone of 3 D-SiP,which enables the vertical stacking and electrical interconnection of electronic *** originated from through-hole(TH) in PCB substrates and evolved in different substrate materials,such as silicon,glass,ceramic,and *** work provides a comprehensive review of four distinguishing TXV technologies(through silicon via(TSV),through glass via(TGV),through ceramic via(TCV),and through mold via(TMV)),including the fabrication mechanisms,processes,and *** TXV technology has unique characteristics and owns particular processes and *** process methods,key technologies,application fields,and advantages and disadvantages of each TXV technology were *** cutting-edge through-hole process and development direction were reviewed.

关键词： through silicon via(TSV) through ceramic via(TCV) through glass via(TGV) through mold via(TMV) 3D packaging chip stacking interposer

在线全文

学校读者我要写书评

暂无评论

DDR5仿真精度研究及在内存升级中的应用

电子技术应用 2023年第8期49卷 53-58页

作者：黄刚姜杰吴均深圳市一博科技股份有限公司广东深圳518051

使用Cadence公司的SystemSI对DDR信号通道进行整体仿真,同时,借助一博科技自研的interposer夹具进行测试,经过多次的仿真测试拟合,所介绍的DDR仿真测试方法可以达到较高的精度。随着对内存带宽的需求不断提升,作为当前主流的DDR4局限性... 详细信息

使用Cadence公司的SystemSI对DDR信号通道进行整体仿真,同时,借助一博科技自研的interposer夹具进行测试,经过多次的仿真测试拟合,所介绍的DDR仿真测试方法可以达到较高的精度。随着对内存带宽的需求不断提升,作为当前主流的DDR4局限性日益明显,通过具体案例说明了DDR5信号完整性提升的具体技术,并通过仿真对比,展示了DDR5在内存升级过程中的优势。

关键词： DDR4 DDR5 SystemSI interposer DFE ODT

Amkor的2.5D和HDFO封装-先进异构芯片封装解决方案

在线全文

学校读者我要写书评

暂无评论

中国集成电路 2018年第12期27卷 71-75,79页

作者：李吕祝 Mike Kelly Amkor Technology大中华区市场及销售部 Amkor Technology Inc.

科技的大浪潮,正向人工智能、深度学习、云端计算、超级电脑等领域快速发展,而这些前沿技术都有一个共同特点,那就是超高性能的高速芯片(IC)。除了主芯片自身往更先进的工艺节点推进外,还可能与更高带宽的内存(High Bandwidth Memory,HB... 详细信息

科技的大浪潮,正向人工智能、深度学习、云端计算、超级电脑等领域快速发展,而这些前沿技术都有一个共同特点,那就是超高性能的高速芯片(IC)。除了主芯片自身往更先进的工艺节点推进外,还可能与更高带宽的内存(High Bandwidth Memory,HBM),或更高传输速度的串行解串器(Serdes),或其它特定功能的芯片,整合成异构芯片封装(Heterogeneous Package),将整体效能推向极致。为了实现这样的功能,异构芯片集成的封装技术将扮演至关重要的角色。本文介绍由Amkor开发的封装技术平台,包括2.5D硅通孔(TSV)介质层(interposer)、基板上芯片(CoS)、晶圆上芯片(CoW)、高密度扇出型封装(HDFO),以及电子设计自动化(EDA)设计流程和测试解决方案。为了达到大规模生产此类先进封装的能力,文章还将介绍最先进的高洁净度高自动化封装工厂K5,以高技术和高质量帮助客户实现其高速性能的目标。

关键词： 2.5D TSV interposer CoS CoW HDFO Heterogeneous Package Amkor