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A Novel Design of Octal-Valued Logic full adder Using Light Color State Model

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Computers, Materials & Continua 2021年第6期67卷 3487-3503页

作者： Ahmed Talal Osama Abu-Elnasr Samir Elmougy Department of Computer Science Faculty of Computes and InformationMansoura UniversityMansoura35516Egypt

Due to the demand of high computational speed for processing big data that requires complex data manipulations in a timely manner,the need for extending classical logic to construct new multi-valued optical models becomes a challenging and promising research *** paper establishes a novel octal-valued logic design model with new optical gates construction based on the hypothesis of Light Color State Model to provide an efficient solution to the limitations of computational processing inherent in the electronics *** provide new mathematical definitions for both of the binary OR function and the PLUS operation in multi valued logic that is used as the basis of novel construction for the optical full adder *** case studies were used to assure the validity of the proposed *** cases proved that the proposed optical 8-valued logic models provide significantly more information to be packed within a single bit and therefore the abilities of data representation and processing is increased.

关键词： Mathematical modeling numerical simulations optical logic optics in computing multi-valued logic full adder

An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending

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Frontiers of Information Technology & Electronic Engineering 2022年第6期23卷 950-965页

作者： Ayoub SADEGHI Nabiollah SHIRI Mahmood RAFIEE Mahsa TAHGHIGH Department of Electrical Engineering.ShirazBranch Islamic Azad UniversityShiraz 71987-74731Iran

We present a new counter-based Wallace-tree(CBW)8×8 *** multiplier’s counters are implemented with a new hybrid full adder(FA)cell,which is based on the transmission gate(TG)*** proposed FA,TG-based AND gate,and hybrid half adder(HA)generate M:3(4≤M≤7)digital counters with the ability to save at least 50%area *** by 90 nm technology prove the superiority of the proposed FA and digital counters under different conditions over the state-of-the-art *** using the proposed cells,the CBW multiplier exhibits high driving capability,low power consumption,and high *** CBW multiplier has a 0.0147 mm^(2)die area in a *** post-layout extraction proves the accuracy of experimental *** image blending mechanism is proposed,in which a direct interface between MATLAB and HSPICE is used to evaluate the presented CBW multiplier in image processing *** peak signal-to-noise ratio(PSNR)and structural similarity index metric(SSIM)are calculated as image quality parameters,and the results confirm that the presented CBW multiplier can be used as an alternative to designs in the literature.

关键词： full adder Transmission gate Counter Multiplier Three-dimensional layout Image blending

Introducing scalable 1-bit full adders for designing quantum-dot cellular automata arithmetic circuits

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Frontiers of Information Technology & Electronic Engineering 2022年第8期23卷 1264-1276页

作者： Hamideh KHAJEHNASIR-JAHROMI Pooya TORKZADEH Massoud DOUSTI Department of Electrical and Computer Engineering Science and Research BranchIslamic Azad UniversityTehran ***Iran

Designing logic circuits using complementary metal-oxide-semiconductor(CMOS)technology at the nano scale has been faced with various challenges *** leakage currents,the short-effect channel,and high energy dissipation are some of the ***-dot cellular automata(QCA)represent an appropriate alternative for possible CMOS replacement in the future because it consumes an insignificant amount of energy compared to the standard *** key point of designing arithmetic circuits is based on the structure of a 1-bit full adder.A low-complexity full adder block is beneficial for developing various intricate *** paper represents scalable 1-bit QCA full adder structures based on cell *** proposed full adders encompass preference aspects of QCA design,such as a low number of cells used,low latency,and small area ***,the proposed structures have been expanded to larger circuits,including a 4-bit ripple carry adder(RCA),a 4-bit ripple borrow subtractor(RBS),an add/sub circuit,and a 2-bit array *** designs were simulated and verified using QCA Designer-E version *** tool can estimate the energy dissipation as well as evaluate the performance of the *** results showed that the proposed designs are efficient in complexity,area,latency,cost,and energy dissipation.

关键词： Quantum-dot cellular automata(QCA) full adder Ripple carry adder(RCA) Add/sub circuit Multiplier

Performance Measurement of Energy Efficient and Highly Scalable Hybrid adder

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Computer Systems Science & Engineering 2023年第6期45卷 2659-2672页

作者： B.Annapoorani P.Marikkannu Anna University Regional Campus CoimbatoreTamilnaduIndia

The adders are the vital arithmetic operation for any arithmetic operations like multiplication,subtraction,and *** number additions are performed by the digital circuit known as the *** VLSI(Very Large Scale Integration),the full adder is a basic component as it plays a major role in designing the integrated circuits *** minimize the power,various adder designs are implemented and each implemented designs undergo defined *** designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is *** overcome such issues and to obtain better performance,a novel parallel adder is *** design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its *** proposed novel parallel adder is attained from the carry look-ahead *** merits of this suggested adder are better speed,power consumption and delay,and the capability in *** designed adders are verified for different supply,delay,power,leakage and its performance is found to be superior to competitive Manchester Carry Chain adder(MCCA),Carry Look Ahead adder(CLAA),Carry Select adder(CSLA),Carry Select adder(CSA)and other adders.

关键词： VLSI full adder carry look ahead adder novel parallel adder

Efficient 16 Boolean logic and arithmetic based on bipolar oxide memristors

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Science China(Information Sciences) 2020年第10期63卷 203-210页

作者： Rui YUAN Mingyuan MA Liying XU Zhenhua ZHU Qingxi DUAN Teng ZHANG Yu ZHU Yu WANG Ru HUANG Yuchao YANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Department of Micro/NanoelectronicsPeking University Department of Electronic Engineering Beijing National Research Center for Information Science and TechnologyTsinghua University Center for Brain Inspired Chips Academy for Artificial IntelligencePeking University Frontiers Science Center for Nano-optoelectronics Peking University

The physically separated memory and logic units in traditional von Neumann computers place essential limits on the performance and cause increased energy consumption, and hence in-memory computing is required to overcome this bottleneck. Here, a new bipolar memristor based in-memory logic approach is proposed, which is capable of achieving all 16 possible Boolean logic functions in a single device in less than3 steps. This approach does not require initialization and can facilitate logic cascading, and the calculation taking place in-situ is showcased by 1-bit full adder and 2-bit multiplier with improved efficiency, thus showing a great prospect in future in-memory computing architecture.

关键词： memristor nonvolatile logic in-memory computing full adder multiplier

Study and Evaluation in CMOS full adders

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Transactions of Tianjin University 2003年第1期9卷 54-57页

作者：陈国章陈昊何丕廉 DepartmentofComputerScienceandEngineering TianjinInstituteofTechnology DepartmentofComputerScienceandInformationEngineering TianjinUniversityofScienceandTechnology SchoolofElectronicInformationEngineering TianjinUniversity

Low power adder circuits, SERF, 10T Ⅰ,10T Ⅱ,10T Ⅲ and a complementary adder (28T) at physical layout level are evaluated. Simulations based on the extracted adder circuit layouts are run to assess how various circuit setups can impact the speed and power consumption. In addition, impacts of output inverters on the circuit performance of modified SERF and 10T adders due to threshold loss problem are also examined. Differences among these adders are addressed and applications of these adders are suggested.

关键词： CMOS full adder 28T adder

Optical Arithmetic Operation Using Optical Demultiplexer

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Circuits and Systems 2016年第11期7卷 3485-3493页

作者： Dilip Kumar Gayen Department of Computer Science & Engineering College of Engineering & Management Kolaghat India

Using Terahertz Optical Asymmetric Demultiplexer (TOAD) based switch we have designed all-optical parallel half adder and full adder. The approach to design this all-optical arithmetic circuit not only enhances the computational speed but also is capable of synthesizing light as input to produce desire output. The main advantage of parallel circuit is synchronization of input which is not required. All the circuits are designed theoretically and verified through numerical simulations.

关键词： Terahertz Optical Asymmetric Demultiplexer Semiconductor Optical Amplifier Half adder full adder Optical Logic