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A 2-to-2.4-GHz differentially-tuned fractional-N frequency synthesizer for DVB tuner applications

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Journal of Semiconductors 2010年第7期31卷 108-114页

作者：孟令部卢磊赵薇唐长文 State Key Laboratory of ASIC & System Fudan University

This paper describes the design of a fractional-N frequency synthesizer for digital video broadcasting-terrestrial （DVB-T） *** functions in differentially-tuned PLL are derived and loop parameters are designed. In addition,a fully-differential charge pump is *** 8/9 high speed prescaler is analyzed and the design considerations for the CML logic are also *** results show that the RMS phase error is less than 0.7°in integer-N mode and less than 1°in fractional-N *** implemented frequency synthesizer draws 10 mA from a 1.8-V supply while occupying a die area of about 1-mm^2 in a 0.18-μm CMOS process.

关键词： frequency synthesizer fully-differential phase noise charge pump

A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

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Journal of Semiconductors 2011年第7期32卷 108-114页

作者：李振荣庄奕琪李兵靳刚 Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices School of MicroelectronicsXidian University

A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18μm CMOS technology.A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance.A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature（I/Q） local oscillating signal.A high-speed 8/9 dual-modulus prescaler（DMP）,a programmable-delay phase frequency detector without dead-zone problem,and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz,and the phase noise is-98.53 dBc/Hz at 100-kHz offset and -121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power *** total area of the receiver is 2.4×1.6 mm^2.

关键词： Beidou receiver frequency synthesizer voltage-controlled oscillator quadrature output divider phase noise

A 4 GHz quadrature output fractional-N frequency synthesizer for an IR-UWB transceiver

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Journal of Semiconductors 2010年第3期31卷 74-79页

作者：郭诗塔黄鲁袁海泉冯立松刘志明 Department of Electronic Science and Technology University of Science and Technology of China

This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal ＆ RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order ∑-△ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is -116 dBc/Hz at 3 MHz offset for a 4 GHz output. Measured spurious tones are lower than -60 dBc. The settling time is within 80°s. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.

关键词： frequency synthesizer dual-modulus prescaler ∑-△ modulator QVCO

A wideband frequency synthesizer for a receiver application at multiple frequencies

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Journal of Semiconductors 2010年第3期31卷 80-84页

作者：王小松黄水龙陈普锋雷牡敏李志强张海英 Institute of Microelectronics Chinese Academy of Sciences

An integer-N frequency synthesizer for a receiver application at multiple frequencies was implemented in 0.18μm 1P6M CMOS technology. The synthesizer generates 2.57 GHz, 2.52 GHz, 2.4 GHz and 2.25 GHz local signals for the receiver. A wide-range voltage-controlled oscillator （VCO） based on a reconfigurable LC tank with a binaryweighted switched capacitor array and a switched inductor array is employed to cover the desired frequencies with a sufficient margin. The measured tuning range of the VCO is from 1.76 to 2.59 GHz. From the carriers of 2.57 GHz, 2.52 GHz, 2.4 GHz and 2.25 GHz, the measured phase noises are -122.13 dBc/Hz, -122.19 dBc/Hz, -121.8 dBc/Hz and -121.05 dBc/Hz, at 1 MHz offset, respectively. Their in-band phase noises are -80.09 dBc/Hz, -80.29 dBc/Hz, -83.05 dBc/Hz and -86.38 dBc/Hz, respectively. The frequency synthesizer including buffers consumes a total power of 70 mW from a 2 V power supply. The chip size is 1.5 × 1 mm2.

关键词： MOS phase locked loop frequency synthesizer multiple frequencies wideband phase noise

A fast lock frequency synthesizer using an improved adaptive frequency calibration

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Journal of Semiconductors 2010年第6期31卷 131-136页

作者：阴亚东阎跃鹏梁伟伟杜占坤 Institute of Microelectronics Chinese Academy of Sciences

An improved adaptive frequency calibration（AFC） has been employed to implement a fast lock phaselocked loop based frequency synthesizer in a 0.18μm CMOS *** AFC can work in two modes：the frequency calibration mode and the store/load *** the frequency calibration mode,a novel frequency-detector is used to reduce the frequency calibration time to 16 us *** the store/load mode,the AFC makes the voltage-controlled oscillator（VCO） return to the calibrated frequency in about 1μs by loading the calibration result stored after the frequency *** experimental results show that the VCO tuning frequency range is about 620-920 MHz and the in-band phase noise within the loop bandwidth of 10 kHz is-82 dBc/*** lock time is about 20μs in frequency calibration mode and about 5 us in store/load *** synthesizer consumes 12 mA from a single 1.8 V supply voltage when steady.

关键词： adaptive frequency calibration frequency detector frequency synthesizer phase-locked loop

A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction

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Journal of Semiconductors 2009年第4期30卷 101-105页

作者：颜小舟邝小飞吴南健 State Key Laboratory for Superlattices and Microstructures Institute of Semiconductors Chinese Academy of Sciences

This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixedsignal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time. An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. The digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. A 1.2 GHz integer-N synthesizer with 1 MHz reference input was implemented in a 0.18 μm process. The measured results demonstrate that the typical settling time of the synthesizer is less than 3 μs, and the phase noise is –108 dBc/Hz@1MHz. The reference spur is –52 dBc.

关键词： fast-settling frequency synthesizer process variation compensation spur reduction

A dual-band frequency synthesizer for CMMB application with low phase noise

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Journal of Semiconductors 2010年第9期31卷 68-73页

作者：于鹏颜峻石寅代伐 Institute of Semiconductors Chinese Academy of Sciences Department of Electrical & Computer Engineering Auburn University

A wide-band frequency synthesizer with low phase noise is *** frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency *** PLL is fabricated with 0.35μm SiGe BiCMOS *** measured result shows that the RMS phase error is less than 1°and the reference spur is less than -60 *** proposed PLL consumes 20 mA current from a 2.8 V *** silicon area occupied without PADs is 1.17 mm;.

关键词： CMMB PLL frequency synthesizer phase noise sigma-delta modulator

A fast-hopping 3-band CMOS frequency synthesizer for MB-OFDM UWB system

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Journal of Semiconductors 2009年第9期30卷 79-85页

作者：郑永正夏玲琍李伟男黄煜梅洪志良 State Key Laboratory of ASIC & System Fudan University

A fast-hopping 3-band （mode 1） multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer is presented. This synthesizer uses two phase-locked loops for generating steady frequencies and one quadrature single-sideband mixer for frequency shifting and quadrature frequency generation. The generated carriers can hop among 3432 MHz, 3960 MHz, and 4488 MHz. Implemented in a 0.13 μm CMOS process, this fully integrated synthesizer consumes 27 mA current from a 1.2 V supply. Measurement shows that the out-of-band spurious tones are below -50 dBc, while the in-band spurious tones are below -34 dBc. The measured hopping time is below 2 ns. The core die area is 1.0 ×1.8 mm^2.

关键词： frequency synthesizer phase-locked loop ultra-wideband CMOS

A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver

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Journal of Semiconductors 2010年第3期31卷 85-89页

作者：肖时茂于云丰马成炎叶甜春殷明 Institute of Microelectronics Chinese Academy of Sciences Hangzhou Zhongke Microelectronics Co Ltd

The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented. The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank, which reduces the power consumption and obtains better phase noise performance. The circuit is validated by simulations and fabricated in a standard 0.18 μm 1P6M CMOS process. Close-loop phase noise measured is lower than -95 dBc at 200 kHz offset while the measured ttming range is 21.5% from 1.47 to 1.83 GHz. The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply. The whole silicon required is only 0.53 mm2.

关键词： CMOS GNSS dual-modulus voltage-controlled oscillator frequency synthesizer