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Design and optimization of CMOS LNA with esd protection for 2.4 GHz WSN application

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Journal of Semiconductors 2011年第10期32卷 103-112页

作者：李智群陈亮张浩 Institute of RF-& OE-ICs Southeast University RFIC and System Engineering Research Center of Ministry of Education of China Southeast University Research Center of Sensor Network Technology Southeast University

A new optimization method of a source inductive degenerated low noise amplifier（LNA） with electrostatic discharge protection is *** can achieve power-constrained simultaneous noise and input matching. An analysis of the input impedance and the noise parameters is also *** on the developed method,a 2.4 GHz LNA for wireless sensor network application is designed and optimized using 0.18-μm RF CMOS technology. The measured results show that the LNA achieves a noise figure of 1.59 dB,a power gain of 14.12 dB, an input 1 dB compression point of-8 dBm and an input third-order intercept point of 1 *** DC current is 4 mA under a supply of 1.8 V.

关键词： LNA esd protection noise and input impedance matching CMOS

Co-design of esd protection and UWB RF front-end ICs

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Science China(Information Sciences) 2011年第10期54卷 2209-2220页

作者： WANG Albert Department of Electrical Engineering University of CaliforniaRiverside 92521USA

This paper discusses critical aspects for co-design of ultra wideband (UWB) system-on-chip (SoC) and on-chip electrostatic discharge (esd) protection,which are beyond the considerations on data rate and *** radio UWB system architecture has been defined with critical building blocks proposed and verified,including pulse generator,transmitter,low noise amplifier (LNA) and multiplier based *** protection is well considered for each related *** examples have been implemented in a commercial RFCMOS processes to demonstrate the working principles for key UWB transmitter and receiver circuit ***-esd co-design techniques,simulation and measurement results for these UWB RF modules are presented in detail.

关键词： UWB impulse radio pulse generator BPSK modulation transmitter LNA multiplier correlator esd protection co-design

Whole-Chip esd protection Design for RF and AMS ICs

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Tsinghua Science and Technology 2010年第3期15卷 265-274页

作者： Xin WANG Siqiang FAN Hui ZHAO Lin LIN Qiang FANG He TANG Albert WANG Department of Electrical Engineering University of California Riverside CA 92521 USA Freescale Semiconductor Inc. Irvine CA 92618 USA

As integrated circuits （IC） technologies advance into very-deep-sub-micron （VDSM）, electrostatic discharge （esd） failure becomes one of the most devastating IC reliability problems and on-chip esd protection design emerges as a major challenge to radio frequency （RF）, analog, and mixed-signal （AMS） IC designs. This paper reviews key design aspects and recent advances in whole-chip esd protection designs for RF/AMS IC applications in CMOS technologies.

关键词： electrostatic discharge (esd) esd protection radio frequency (RF) parasitic capacitance

Emerging Challenges in esd protection for RF ICs in CMOS

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Journal of Semiconductors 2008年第4期29卷 628-636页

作者：王自惠林琳王昕刘海南周玉梅 Department of Electrical Engineering University of CaliforniaRiversideCA 92521USA 中国科学院微电子研究所

On-chip electrostatic discharge （esd） protection design has become an emerging challenge for radio-frequency （RF） integrated circuits （IC） design as IC technologies migrate into the very-deep-sub-micron （VDSM） regime and RF ICs move into multi-GHz operations. The key problem originates from the complex interaction between the esd protection circuitry and the core RF IC circuit under protection. This paper discusses the recent development in RF esd protection research and design,outlining emerging challenges, new design methods,and novel RF esd protection solutions.

关键词： electrostatic discharge esd protection RF esd parasitic

On a Parasitic Bipolar Transistor Action in a Diode esd protection Device

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Circuits and Systems 2016年第9期7卷 2286-2295页

作者： Jin Young Choi Department of Electronic & Electrical Engineering Hongik University Sejong Korea

In this work, we show that an excessive lattice heating problem can occur in the diode electrostatic discharge (esd) protection device connected to a VDD bus in the popular diode input protection scheme, which is favorably used in CMOS RF ICs. To figure out the reason for the excessive lattice heating, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-D device simulator. We analyze the simulation results in detail to show out that a parasitic pnp bipolar transistor action relating nearby p+-substrate contacts is responsible for the excessive lattice heating in the diode protection device, which has never been focused before anywhere.

关键词： esd protection Diode protection Device Bipolar Transistor Mixed-Mode Simulation RF IC

Design and investigation of novel ultra-high-voltage junction field-effect transistor embedded with NPN

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Chinese Physics B 2021年第7期30卷 619-623页

作者： Xi-Kun Feng Xiao-Feng Gu Qin-Ling Ma Yan-Ni Yang Hai-Lian Liang Engineering Research Center of Internet of Things Technology Applications(Ministry of Education) Department of Electronic EngineeringJiangnan UniversityWuxi 214122China

Ultra-high-voltage(UHV)junction field-effect transistors(JFETs)embedded separately with the lateral NPN(JFETLNPN),and the lateral and vertical NPN(JFET-LVNPN),are demonstrated experimentally for improving the electrostatic discharge(esd)*** esd characteristics show that both JFET-LNPN and JFET-LVNPN can pass the 5.5-k V human body model(HBM)*** JFETs embedded with different NPNs have 3.75 times stronger in esd robustness than the conventional *** failure analysis of the devices is performed with scanning electron microscopy,and the obtained delayer images illustrate that the JFETs embedded with NPN transistors have good voltage endurance ***,the internal physical mechanism of the JFETs embedded with different NPNs is investigated with emission microscopy and Sentaurus simulation,and the results confirm that the JFET-LVNPN has stronger esd robustness than the JFET-LNPN,because the vertical NPN has a better electron collecting *** JFET-LVNPN is helpful in providing a strong esd protection and functions for a power device.

关键词： junction field-effect transistors NPN electrostatic discharge(esd)robustness esd protection

An IO block array in a radiation-hardened SOI SRAM-based FPGA

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Journal of Semiconductors 2012年第1期33卷 137-143页

作者： Zhao Yan Wu Lihua Han Xiaowei Li Yan Zhang Qianli Chen Liang Zhang Guoquan Li Jianzhong Yang Bo Gao Jiantou Wang Jian Li Ming Liu Guizhai Zhang Feng Guo Xufeng Zhao Kai Stanley L.Chen Yu Fang Liu zhongli Institute of Semiconductors Chinese Academy of Sciences Beijing 100083China

We present an input/output block （lOB） array used in the radiation-hardened SRAM-based field- programmable gate array （FPGA） VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator （SOI） logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an esd protection network. A boundary-scan path circuit can be used between the pro- grammable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The esd protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different ca- pacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS 1000 chip with an IOB array has a total dose tolerance of 100 krad（Si）, a dose survivability rate of 1.5 × 10^11 rad（Si）/s, and a neutron fluence immunity of 1×10^14 n/cm2.

关键词： partially-depleted SOI FPGA IOB radiation-hardened esd protection

Low power 3.1–10.6 GHz IR-UWB transmitter for Gbps wireless communications

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Science China(Information Sciences) 2011年第5期54卷 1094-1102页

作者： WANG Albert ZHANG Gary Department of Electrical Engineering University of California Riverside 92521 USA Skyworks Solutions Inc. Irvine CA USA

This paper reviews and discusses the design of a low-power single-full-band (3.1-10.6 GHz) non- carrier impulse-radio ultra wideband (UWB) transmitter featuring 5th-order Gaussian derivative pulse shaping, integrated BPSK modulation, and 2.5 kV whole-chip esd (electrostatic discharge) protection. The UWB transmitter design has been implemented in a commercial 0.18 μm CMOS technology with a very small die size of 0.25 mm2. The fabricated chips have demonstrated full functionality, extremely low power consumption of 0.14 pJ/p-mV, and an ultra short pulse width of 394 ps. This esd-protected UWB transmitter has the potential to support wireless streaming to gigabit per second (Gbps).

关键词： UWB impulse radio BPSK transmitter esd protection

A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail esd clamp

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Journal of Semiconductors 2013年第1期34卷 53-57页

作者：潘红伟刘斯扬孙伟锋 National ASIC System Engineering Research Center Southeast University

The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail esd（electro-static discharge） clamp *** order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown *** device has been validated using TLP measurement analysis and is applied to a power-rail esd clamp in half-bridge driver ICs.

关键词： esd protection esd robustness SCR-LDMOS latch-up holding voltage