A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp

作     者：潘红伟 刘斯扬 孙伟锋 

作者机构：National ASIC System Engineering Research CenterSoutheast University 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2013年第34卷第1期

页      面：53-57页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程（可授工学、理学学位）] 080502[工学-材料学] 

基　　金：Project supported by the Natural Science Foundation of Jiangsu Province (No.BK2011059) the Program for New Century Excellent Talent in University (No.NCET-10-0331) 

主　　题：ESD protection ESD robustness SCR-LDMOS latch-up holding voltage 

摘      要：The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp *** order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown *** device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.