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3d resistive RAM cell design for high-density storage class memory—a review

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Science China(Information Sciences) 2016年第6期59卷 35-55页

作者： Boris HUdEC Chung-Wei HSU I-Ting WANG Wei-Li LAI Che-Chia CHANG Taifang WANG Karol FRHLICH Chia-Hua HO Chen-Hsi LIN Tuo-Hung HOU department of Electronics Engineering and Institute of Electronics National Chiao-Tung University Institute of Electrical Engineering Slovak Academy of Sciences Winbond Electronics Corporation

In this article, we comprehensively review recent progress in the Re RAM cell technology for 3D integration focusing on a material/device level. First we briefly mention pioneering work on high-density crossbar Re RAM arrays which paved the way to 3D integration. We discuss the two main proposed 3D integration schemes—3d horizontally stacked Re RAM vs 3d Vertical Re RAM and their respective advantages and disadvantages. We follow with the detailed memory cell design on important work in both areas, utilizing either filamentary or interface-limited switching mechanisms. We also discuss our own contributions on Hf O2-based filamentary 3d Vertical Re RAM as well as Ta Ox/Ti O2 bilayer-based self-rectifying 3d Vertical Re RAM. Finally,we summarize the present status and provide an outlook for the nearterm future.

关键词： RRAM ReRAM resistive switching crossbar cross-point storage class memory 3D integration atomic layer deposition selector

design of a 3d Wilkinson power divider using through glass via technology

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Journal of Semiconductors 2018年第12期39卷 197-200页

作者： Jifei Sang Libo Qian Yinshui Xia Huakang Xia Faculty of Electrical Engineering and Computer Science Ningbo University

due to its low electrical loss and low process cost, a glass interposer has been developed to provide a compelling alternative to the silicon-based interposer for packaging of future 2-d and 3-d ICs. In this study,through glass vias(TGVs) are used to implement 3-d inductors for minimal footprint and large quality factor. Using the inductors and parallel plate capacitors, a compact 3-d Wilkinson power divider is designed and analyzed.Compared with some reported power dividers, the proposed TGV-based circuit has an ultra-compact size and excellent electrical performance.

关键词： 3D integration glass interposer through glass vias power divider

Integrated 3d Fan-out Package of RF Microsystem and Antenna for 5G Communications

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ZTE Communications 2020年第3期18卷 33-41页

作者： XIA Chenhui WANG Gang WANG Bo MING Xuefei The 58th Research Institute of China Electronics Technology Group Corporation Wuxi 214000China

A 3d fan-out packaging method for the integration of 5G communication RF microsystem and antenna is studied.First of all,through the double-sided wiring technology on the glass wafer,the fabrication of 5G antenna array is realized.Then the low power devices such as through silicon via(TSV)transfer chips,filters and antenna tuners are flip-welded on the glass wafer,and the glass wafer is reformed into a wafer permanently bonded with glass and resin by the injection molding process with resin material.Finally,the thinning resin surface leaks out of the TSV transfer chip,the rewiring is carried out on the resin surface,and then the power amplifier,low-noise amplifier,power management and other devices are flip-welded on the resin wafer surface.A ball grid array(BGA)is implanted to form the final package.The loss of the RF transmission line is measured by using the RF millimeter wave probe table.The results show that the RF transmission loss from the chip end to the antenna end in the fan-out package is very small,and it is only 0.26 dB/mm when working in 60 GHz.A slot coupling antenna is designed on the glass wafer.The antenna can operate at 60 GHz and the maximum gain can reach 6 dB within the working bandwidth.This demonstration successfully provides a feasible solution for the 3d fan-out integration of RF microsystem and antenna in 5G communications.

关键词： AiP fan‐out package RF microsystem 3D integration 5G communications

Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips

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Journal of Semiconductors 2014年第1期35卷 121-128页

作者：刘晓贤朱樟明杨银堂王凤娟丁瑞雪 School of Microelectronics Xidian University Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices

In high speed three-dimensional integrated circuits （3d ICs）, through silicon via （TSV） insertion causes impedance discontinuities along the interconnect-TSV channel that results in signal reflection. As demonstrated for a two-plane interconnect structure connected by a TSV, we incorporate an appropriate capacitance at the junction to mitigate the signal reflection with gigascale frequencies. Based on 65 nm technology and S-parameter analysis, the decrease of signal reflection can be 189% at the tuned frequency of 5 GHz. Extending this method to the five-plane interconnect structure further, the reduction of signal reflection can achieve 400%. So we could broaden this method to any multilevel 3d interconnect structures. This method can also be applied to a circuit with tunable operating frequencies by digitally connecting the corresponding matching capacitance into the circuit through switches. There are remarkable improvements of the quality of the transmitting signals.

关键词： 3D integration TSV signal reflection impedance matching S-parameter

Looking into the future of Nanoelectronics in the diversification Efficient Era

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Science China(Information Sciences) 2016年第6期59卷 6-19页

作者： Simon dELEONIBUS Universit′es Grenoble Alpes CEA LETIMINATEC Campus

The linear scaling of CMOS has encountered, since its beginning, many hurdles which request new process modules, driven mainly by the maximization of energy efficiency. Fabrication at the sub 10 nm node level will request Intrinsic Variability approaching to zero. The rapid growth of mobile, multifunctional and autonomous systems is hardly demanding to reach Zero Power consumption. The solutions to integrate Thin Film based devices, architectures and systems in order to face these challenges are described.

关键词： CMOS thin films heterogeneous integration NEMS 3D integration sequential parallel zero intrinsic variability zero power systems

Analysis and optimization of TSV–TSV coupling in three-dimensional integrated circuits

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Journal of Semiconductors 2015年第4期36卷 172-179页

作者：赵颖博董刚杨银堂 School of Microelectronics Xidian UniversityKey Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices

Through silicon via （TSV）-TSV coupling is detrimental to the performance of three-dimensional （3d） integrated circuits （ICs） with the major negative effect of introducing coupling noise. In order to obtain an accurate estimation of the coupling level from TSV-TSV in the early design stage, this paper first proposes an impedance- level model of the coupling channel between TSVs based on a two-port network, and then derives the formula of the coupling coefficient to describe the TSV-TSV coupling effect. The accuracy of the formula is validated by comparing the results with 3d full-wave simulations. Furthermore, a design technique for optimizing the coupling between adjacent coupled signal TSVs is proposed. Through SPICE simulations, the proposed technique shows its feasibility to reduce the coupling noise for both a simple TSV-TSV circuit and a complicated circuit with more TSVs, and demonstrates its potential for designers in achieving the goal of improving the electrical pertbrmance of3d ICs.

关键词： 3D integration though silicon vias （TSVs） two-port network equivalent impedance noise couplingreduction

Interconnects for nanoscale MOSFET technology:a review

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Journal of Semiconductors 2013年第6期34卷 157-164页

作者： Amit Chaudhry UIET Panjab University

In this paper,a review of Cu/low-k,carbon nanotube（CNT）,graphene nanoribbon（GNR）and optical based interconnect technologies has been done,Interconnect models,challenges and solutions have also been discussed.Of all the four technologies,CNT interconnects satisfy most of the challenges and they are most suited for nanometer scale technologies,despite some minor drawbacks.It is concluded that beyond 32nm technology,a paradigm shift in the interconnect material is required as Cu/low-k interconnects are approaching fundamental limits.

关键词： Cu/low-k 3D integration electromigration CNTs graphene interconnects comparisons