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Motion simulation and test on threshed grains in tapered threshing and transmission device for plot wheat breeding based on CFD-DEM

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International Journal of Agricultural and Biological Engineering 2019年第1期12卷 66-73页

作者： Fei Dai Xuefeng Song Wuyun Zhao zhengsheng han Fengwei Zhang Shilin Zhang College of Mechanical and Electrical Engineering Gansu Agricultural UniversityLanzhou 730070China

Mechanization of field experiments is the only way to improve crop breeding and seed propagation *** order to further clarify and improve the working performance of tapered threshing device for plot breeding,and reduce the remaining seeds in the device,the numerical simulation was carried out on the motion process of materials in the longitudinal-axial tapered cylinder threshing and transmission device of the plot wheat breeding combine harvester based on CFD-DEM *** results showed that,threshing and transmission of particles and short stalks at axial direction could be realized under the influence of air ***,the material transference and distribution rule and stream field distribution rule of air flow in the threshing and transmission device were obtained,the variations of velocity and displacement of particles and short stalks with time were obtained;the motion trajectories and forms of particles in different types of retention were also *** rotating speed of 1300-1600 r/min for the tapered threshing cylinder in the verification test,the particle retention rate in the enclosure was 0-0.13%,while in the simulation the particle retention rate in the enclosure was 0-0.11%,only a 0.02%difference between *** results proved a favorable feasibility to simulate the working performance of the tapered threshing and transmission device for plot breeding through gas-solid coupling method.

关键词： particle threshing and transmission tapered threshing and transmission device hydromechanics calculation discrete element numerical simulation test

Influence of back-gate stress on the back-gate threshold voltage of a LOCOS-isolated SOI MOSFET

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维普期刊数据库

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Journal of Semiconductors 2012年第2期33卷 36-40页

作者： Mei Bo Bi Jinshun Li Duoli Liu Sinan han zhengsheng Institute of Microelectronics Chinese Academy of SciencesBeijing 100029China

The performance of a LOCOS-isolated SOI MOSFET heavily depends on its back-gate characteristic, which can be affected by back-gate stress.A large voltage stress was applied to the back gate of SOI devices for at least 30 s at room temperature,which could effectively modify the back-gate threshold voltage of these devices. This modification is stable and time *** order to improve the back-gate threshold voltage,positive substrate bias was applied to NMOS devices and negative substrate bias was applied to PMOS *** results suggest that there is a leakage path between source and drain along the silicon island edge,and the application of large backgate bias with the source,drain and gate grounded can strongly affect this leakage *** we draw the conclusion that the back-gate threshold voltage,which is directly related to the leakage current,can be influenced by back-gate stress.

关键词： back-gate threshold voltage stress silicon-on-insulator

A novel SOI-DTMOS structure from circuit performance considerations

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Journal of Semiconductors 2009年第2期30卷 34-38页

作者：宋文斌毕津顺韩郑生 Institute of Microelectronics Chinese Academy of Sciences

The performance of a partially depleted silicon-on-insulator （PDSO1） dynamic threshold MOSFET （DT- MOS） is degraded by the large body capacitance and body resistance. Increasing silicon film thickness can reduce the body resistance greatly, but the body capacitance also increases significantly at the same time. To solve this problem, a novel SOl DTMOSFET structure （drain/source-on-local-insulator structure） is proposed. From ISE simulation, the improvement in delay, obtained by optimizing p-n junction depth and silicon film thickness, is very significant. At the same time, we find that the drive current increases significantly as the thickness of the silicon film increases. Furthermore, only one additional mask is needed to form the local SIMOX, and other fabrication processes are fully compatible with conventional CMOS/SOI technology.

关键词： partially depleted silicon-on-insulator dynamic threshold MOSFET body capacitance body resistance silicon film thickness circuit delay

Single-event burnout hardening of planar power MOSFET with partially widened trench source

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Journal of Semiconductors 2018年第3期39卷 44-49页

作者： Jiang Lu Hainan Liu Xiaowu Cai Jiajun Luo Bo Li Binhong Li Lixin Wang zhengsheng han Institute of Microelectronics of Chinese Academy of Sciences Beijing 100029China Key Laboratory of Silicon Device Technology Chinese Academy of SciencesBeijing 100029China University of Chinese Academy of Sciences Beijing 100029China

We present a single-event burnout（SEB） hardened planar power MOSFET with partially widened trench sources by three-dimensional（3 D） numerical simulation. The advantage of the proposed structure is that the work of the parasitic bipolar transistor inherited in the power MOSFET is suppressed effectively due to the elimination of the most sensitive region（P-well region below the N＋ source）. The simulation result shows that the proposed structure can enhance the SEB survivability significantly. The critical value of linear energy transfer（LET）,which indicates the maximum deposited energy on the device without SEB behavior, increases from 0.06 to0.7 p C/μm. The SEB threshold voltage increases to 120 V, which is 80% of the rated breakdown voltage. Meanwhile, the main parameter characteristics of the proposed structure remain similar with those of the conventional planar structure. Therefore, this structure offers a potential optimization path to planar power MOSFET with high SEB survivability for space and atmospheric applications.

关键词： planar power MOSFETs single-event burnout(SEB) parasitic bipolar transistor second breakdown voltage

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超低压ESD保护器件设计与工艺研究

固体电子学研究与进展 2008年第3期28卷 445-448页

作者：淮永进韩郑生中国科学院微电子研究所北京100029

介绍了一种新颖的超低压保护器件的工作原理、结构特点,并进行了器件结构模拟。结合理论分析与模拟仿真得到超低压1.8～5 V的ESD保护器件系列模型。经过设计与工艺验证,制作出了非常吻合模拟结果的超低压器件,该系列器件具有工作电压低... 详细信息

介绍了一种新颖的超低压保护器件的工作原理、结构特点,并进行了器件结构模拟。结合理论分析与模拟仿真得到超低压1.8～5 V的ESD保护器件系列模型。经过设计与工艺验证,制作出了非常吻合模拟结果的超低压器件,该系列器件具有工作电压低、电容小、漏电小的特点。由于采用新型复合型穿通结构及单片低温减压外延工艺,器件的电参数一致性非常理想,在高速数据线的保护电路中成功地得到应用。

关键词：超低压保护器件静电放电模拟复合型穿通结构瞬态电压抑制器

The ESD protection designed for LDMOS power amplifier

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The ESD protection designed for LDMOS power amplifier

Effect of cryogenic temperature characteristics on 0.18-μm silicon-on-insulator devices

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Jiang Yibo Du Huan Zeng Chuanbin han zhengsheng Silicon device and integration Technology Department The Institute of Microelectronics of Chinese Academy of Sciences

As power amplifier,the LDMOS（Lateral Double diffusion MOS）was exciting due to its high voltage capability, low cost and high integrated ***（Electrostatic-Discharge） damage challenged its reliability and integrated ESD protection was *** paper investigated on effective integrated ESD protection consists of gate-protection,self-protection and reverse-direction *** the parasitic capacitance of ESD protection was extracted through de-embedding.

关键词： ESD(Electrostatic-Discharge) LDMOS(Radio Frequency Lateral Double diffusion MOS) Cascaded NMOS Poly-silicon diode

来源： cnki会议评论

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cnki会议

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Chinese Physics B 2016年第7期25卷 546-552页

作者：解冰清李博毕津顺卜建辉吴驰李彬鸿韩郑生罗家俊 Key Laboratory of Silicon Device and Technology Institute of Microelectronics Chinese Academy of Sciences

The experimental results of the cryogenic temperature characteristics on 0.18-μm silicon-on-insulator（SOI） metaloxide-silicon（MOS） field-effect-transistors（FETs） were presented in detail. The current and capacitance characteristics for different operating conditions ranging from 300 K to 10 K were discussed. SOI MOSFETs at cryogenic temperature exhibit improved performance, as expected. Nevertheless, operation at cryogenic temperature also demonstrates abnormal behaviors, such as the impurity freeze-out and series resistance effects. In this paper, the critical parameters of the devices were extracted with a specific method from 300 K to 10 K. Accordingly, some temperature-dependent-parameter models were created to improve fitting precision at cryogenic temperature.

关键词： cryogenic temperature metal-oxide-semiconductor silicon-on-insulator capacitance

An Analytical Threshold Voltage Model for Fully Depleted SOI MOSFETs

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Journal of Semiconductors 2005年第12期26卷 2303-2308页

作者：李瑞贞韩郑生中国科学院微电子研究所北京100029

A new two-dimensional （2D） analytical model for the threshold-voltage of fully depleted SOI MOSFETs is derived. The 2D potential distribution functions in the active layer of the devices are obtained through solving the 2D Poisson＇s equation. The minimum of the potential at the oxide-Si layer interface is used to monitor the threshold voltage of the SOI MOSFETs. This model is verified by its excellent agreement with MEDICI simulation using SOI MOSFETs with different gate lengths,gate oxide thicknesses,silicon film thicknesses,and channel doping concentrations.

关键词： fully depleted SOI MOSFETs surface potential threshold voltage

基于遗传算法的BSIM SOI模型参数提取

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Journal of Semiconductors 2005年第8期26卷 1676-1680页

作者：李瑞贞韩郑生中国科学院微电子研究所北京100029

提出了一种提取BSIMSOI模型参数的新方法,该方法基于遗传算法和局部优化法的结合,同时具有全局优化和局部优化的优点,提取的参数物理意义明确,并且容易得到全局最优解.该方法计算简单,不需要对模型进行深入了解和丰富的参数提取经验,易... 详细信息

提出了一种提取BSIMSOI模型参数的新方法,该方法基于遗传算法和局部优化法的结合,同时具有全局优化和局部优化的优点,提取的参数物理意义明确,并且容易得到全局最优解.该方法计算简单,不需要对模型进行深入了解和丰富的参数提取经验,易于推广使用.对用该方法得到的SOI模型进行了模拟,并将模拟结果与1.2μmCMOS/SOI测试结果进行对比,二者吻合很好,SOI器件特有的kink效应也得到了很好的拟合.

关键词：遗传算法 SOI 参数提取