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A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

Nuclear Science and Techniques 2022年第7期33卷 49-59页

作者： xiao-Ting Li Wei Wei Ying Zhang Xiong-Bo Yan xiao-shan jiang Ping Yang State Key Laboratory of Particle Detection and Electronics Experimental Physics DepartmentInstitute of High Energy PhysicsChinese Academy of Sciences19B Yuquan RoadBeijing100049China School of Physical Sciences University of Chinese Academy of Sciences19A Yuquan RoadBeijing100049China PLAC Key Laboratory of Quark and Lepton Physics(MOE)Central China Normal University152 Luoyu RoadWuhan430079China

There is an urgent need for high-quality and high-frequency clock generators for high-energy physics *** transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel ***,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these *** study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS *** includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock *** the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy *** proposed VCO uses low-pass filters to suppress the noise from bias *** tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two *** jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,*** LC-PLL consumed 27 mW for the core and 73.8 mW in *** measured results nearly coincided with the simulations and validated the analyses and tests.

关键词： LC phase-locked loop Analog electronic circuits Front-end electronics for detector readout High-energy physics experiments

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FPGA implementation of 10 G Ethernet-based DAQ systems for pixel detectors

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Radiation Detection Technology and Methods 2020年第1期4卷 31-38页

作者： Hang-xu Li Jie Zhang Ye Ding shan-shan Cui Zheng Wang xiao-shan jiang State Key Laboratory of Particle Detection and Electronics Institute of High Energy PhysicsChinese Academy of Sciences(CAS)Beijing 100049China University of Chinese Academy of Sciences(UCAS) Beijing 100049China

Background High Energy Photon Source-Test Facility is a project to study and verify the feasibility of the key technologies which will be applied to that of High Energy Photon Source(HEPS).The pixel array detector is one of the most important components of synchrotron radiation *** In order to meet the requirements of the X-ray detection of HEPS,it was asked to independently develop a pixel array detector prototype with an effective detection area larger than 8×8 cm^(2),a spatial resolution better than 200 pm,a detectable energy range from 8 to 20 keV,and a frame rate higher than 1 *** readout electronics system using the field-programmable gate array(FPGA)as its core of the digital logic makes the basic functions of the detector prototype feasibility by implementing all the configuration and data readout of the BPIX which is the dedicated pixel readout chip designed for Chinese next generation of synchrotron light source and working in the single-photon counting *** the large amount of data generated by pixel detectors and the demand for real-time data acquisition at higher frame rates,a firmware based on the TCP/IP protocol was developed in *** The implementation of 1 G/10 G Ethernet hub firmware provides a method of processing multi-ports Gigabit data and improving *** key idea is the conversion of the GMII/XGMII bus in 1 G/10 G Ethernet protocol and the Arbitrator module applying Round-Robin *** and conclusion The firmware converts and gathers TCP/IP frames from Gigabit network to 10-Gigabit network *** measurement,the bandwidth of the hub can reach 8.57 Gbps.A pixel detector integrated with 1 G/10 G Ethernet hub completes the readout of large flux data on 1.5 mega pixels detector at 1.2 kHz frame rate.

关键词： FPGA TCP/IP 10-Gigabit HEPS

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Reliability study of custom designed ADC for the jiangmen underground neutrino observatory

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Radiation Detection Technology and Methods 2020年第2期4卷 203-207页

作者： Ru-yi Jin Jun Hu Jia-yi Ren Zhe Ning xiao-shan jiang State Key Laboratory of Particle Detection and Electronics Institute of High Energy PhysicsChinese Academy of Sciences(CAS)Beijing 100049China University of Chinese Academy of Sciences(UCAS) Beijing 100049China

Objective The jiangmen underground neutrino observatory(JUNO)is the largest and most precise liquid scintillator detector under construction in the south of *** front-end readout electronics system will be installed very close to the photomultiplier tubes under ***,the system’s absolute reliability is *** an important piece,the failure rate of the custom designed analog-to-digital convertor(ADC)must be *** The Arrhenius High Temperature Operating Life(HTOL)model is usually used to calculate the standard reliability value failure rate(λ).A temperature acceleration test of the ADC is performed with a 115℃ambient temperature based on a custom aging *** performance of ADC is compared before and after aging,and the most significant bit(MSB)of the digital output is monitored during the *** The result of a 2400-hour-long test shows that there were no *** upper limit of the failure rate is calculated as 5.8FIT,which can be added to the failure rate of other components to meet the overall failure rate requirements(84FIT).Conclusion With the test system,we established a method based on the HTOL model to obtain the upper limit of the ADC reliability for overall failure rate calculation in *** method can be applied to the reliability measurement for any other custom designed *** experiment can be repeated with a new set of parameters to get a satisfactory failure rate according to other overall system requirements.

关键词： ADC Reliability HTOL Failure rate

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Study on low noise cryogenic charge readout electronics for liquid xenon time projection chamber

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Radiation Detection Technology and Methods 2021年第1期5卷 71-77页

作者： Xing-cheng Tian xiao-shan jiang Wen-huan Wu Huai-shen Li Wei Wei Jun Hu State Key Laboratory of Particle Detection and Electronics Institute of High Energy PhysicsChinese Academy of Sciences(CAS)Beijing 100049China University of Chinese Academy of Sciences(UCAS) Beijing 100049China China Spallation Neutron Source Institute of High Energy PhysicsChinese Academy of Sciences(CAS)Dongguan 523803China

Background Liquid xenon time projection chamber(LXe TPC)is widely used in high-energy physics experiments such as particle detection and neutrino(or neutrinoless)double beta *** charge readout accuracy of the LXeTPCdirectly affects the measurement results and success of the *** liquid xenon needs to maintain a cryogenic temperature between 162 and 165 K at atmospheric pressure,the charge generated in the LXe TPC always needs to be read out in the cryogenic environment for minimizing the input capacitance,which has effect in determining the output noise of the charge *** Design a charge readout electronics system applicable to LXe TPC and research a data analysis method to get the exact amount of charge by analyzing the waveform at that output of the designed electronics *** Design a multi-channel charge-reading application specific integrated circuit(ASIC)that can operate in the cryogenic *** signals and power supply of the ASIC are connected to an electronics system at room temperature through micro-coaxial *** electronics at room temperature complete the sampling of the ASIC output.A data acquisition device receives the sampled waveform data and calculates the charge measurement resolution by Gaussian *** The designed ASIC and selected micro-coaxial cable can work in stable condition under the cryogenic environment of 165 *** analyzed integral nonlinearity of the charge measurement of the chip is 0.83%in the range from 1 to 50 fC,and the charge measurement resolution of the chip is lower than 900 e−*** In this paper,a preliminary study of the charge readout method based on the system structure of self-developed ASIC,micro-coaxial cable,and data readout electronics is completed for LXe *** system test results indicate that the designed ASIC can work normally in the cryogenic temperature of 165 K with a high dynamic range and good linearity of the charge ***

关键词： nEXO Cryogenic ASIC Micro-coaxial cable Gaussian fitting

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Characterization of FEEWAVE,a low‑power waveform digitizer ASIC with 15‑ps time resolution

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Radiation Detection Technology and Methods 2023年第3期7卷 410-417页

作者： Yu‑sheng Wang Jia‑yi Ren Wei Wei Jie Zhang Pei‑ran Ye xiao‑shan jiang Zheng Wang Institute of High Energy Physics Chinese Academy of Sciences19B Yuquan RdShijingshan DistrictBeijingChina State Key Laboratory of Particle Detection and Electronics of China 19B Yuquan RdShijingshan DistrictBeijingChina University of Chinese Academy of Sciences 19A Yuquan RdShijingshan DistrictBeijingChina Spallation Neutron Source Science Center Zhongziyuan RoadDalangDongguan 523803China

Purpose FEEWAVE is a chip with a waveform digitizer based on a switched capacitor array(SCA).A SCA uses capacitor arrays to store waveforms and exhibits low-power consumption and high time resolution ***,the limitations of the chip manufacturing process induce sampling interval and digitization deviations between different cells,which affects the performance of the *** Calibration was performed on the SCA sampling part on the FEEWAVE chip to obtain more accurate digitized output and time intervals between the sampling *** were carried out according to the proposed amplitude and time calibration methods,and the time resolution of the chip was further improved by a fitting *** and conclusion Through the calibration algorithm,the time resolution of the SCA sampling part of the chip reached 9.0 ps after *** the self-test of the electronics time performance,the time measurement after leading-edge fitting and calibration was approximately 12.3 *** the joint test with silicon photomultiplier detectors,the time resolution of the SCA part was low and comparable to the resolution of the oscilloscope after calibration algorithm and waveform fitting.

关键词： Waveform sampling SCA Calibration

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A high time resolution and low-power ASIC for MRPC applications

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Radiation Detection Technology and Methods 2020年第1期4卷 63-69页

作者： Jia-yi Ren Wei Wei Ru-yi Jin Jie Zhang Gang Liu xiao-shan jiang Zheng Wang State Key Laboratory of Particle Detection and Electronics Institute of High Energy PhysicsChinese Academy of Sciences(CAS)Beijing 100049China University of Chinese Academy of Sciences(UCAS) Beijing 100049China

Purpose The structure of readout circuits needs to be improved to meet the requirements of the endcap time of flight upgrade with multi-gap resistive plate chamber(MRPC)in Beijing SpectrometerⅢexperiments,posing a demand for the high time resolution and low-power *** Considering MRPC features,an application-specific integrated circuit(ASIC)called FEEWAVE,which integrates the front-end circuit and digitization function,is proposed to meet the above *** front-end circuit implements I/V conversion and signal *** reduce power consumption and further improve the time resolution,the waveform sampling technique based on switch capacitor array is *** and conclusion A 30 fC to 1.2 pC input signal dynamic range is obtained,and the jitter is less than 21 ps *** the same time,the chip realizes 5 GSPS(gigabit samples per second)sampling rate,trigger rate capability of 50 kHz and 25 mW/channel power *** 6-channel ASIC has been designed and taped out with 0.18μm complementary metal oxide semiconductor *** preliminary test results of FEEWAVE have been achieved.

关键词： MRPC Waveform sampling ASIC

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Design of a MAPS readout electronics prototype for BESIII inner tracker

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Radiation Detection Technology and Methods 2020年第2期4卷 241-249页

作者： Xing-cheng Tian xiao-shan jiang Jun Hu Qun Ou Yang Ming-yi Dong Chao-yue Qu Xu-dong Ju Hong-yu Zhang Ye Wu xiao-xu Lu State Key Laboratory of Particle Detection and Electronics Institute of High Energy PhysicsChinese Academy of Sciences(CAS)Beijing 100049China University of Chinese Academy of Sciences(UCAS) Beijing 100049China China Spallation Neutron Source Institute of High Energy PhysicsChinese Academy of Sciences(CAS)Dongguan 523803China

Background The spatial resolution and the reconstruction efficiency of the main drift chamber of the Beijing Spectrometer III has degraded aftermore than nine years of *** improved new inner drift chamber has been constructed to replace the old chamber in case of the radiation *** active pixel sensor(MAPS)based detector prototype is selected as one of the prototype schemes for the inner chamber *** Design a set of MAPS readout electronics system for the inner drift chamber *** system can verify the function and performance of the selected MAPS chip and discover the matters needing attention when designing large-scale *** The electronics system design is composed of three *** first part is flexible printed circuit boards(PCBs)assembled with the MAPS *** second part is digital readout boards,which are connected to the flexible PCBs via FPGA mezzanine card *** digital readout board realizes the configuration of the MAPS chip register,receives and processes the data output by the MAPS chip,and transfers the processed data to the DAQ *** third part includes a readout control board and two fan-out boards that used to separately fan out the trigger signal and the start signal to all the digital readout *** and conclusion AMAPS readout electronics system consisting of five MAPS based detector prototypes is *** system can work stably under the electron beam experimental conditions with a frequency up to 2 kHz and energy ranging from 1 to 5 *** system detection efficiency of the electron beam is∼95%,and the spatial resolution is∼5.3μm at electron energies of 1 *** design of the electronics system meets the requirements for verifying the performance of the MAPS chips and the technical feasibility of the detector structure.

关键词： BESIII MAPS pixel detector JTAG FPGA

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The development and application of the test system for the silicon pixel modules in HEPS-BPIX

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Radiation Detection Technology and Methods 2021年第1期5卷 53-60页

作者： Ye Ding Jie Zhang Wei Wei Zhen-jie Li Hang-xu Li xiao-lu Ji Yan Zhang xiao-shan jiang Ke-jun Zhu Peng Liu Yuan-bo Chen Qiu-ju Li Wei-fan Sheng State Key Laboratory of Particle Detection and Electronics Institute of High Energy PhysicsChinese Academy of Sciences(CAS)Beijing 100049China Institute of High Energy Physics Chinese Academy of Sciences19 B Yuquan RdShijingshan DistrictBeijingChina University of Chinese Academy of Sciences(UCAS) Beijing 100049China

Background HEPS-BPIX is a prototype of photon counting pixel detector developed for the High Energy Photon *** consists of 16 silicon pixel modules which should be tested individually to ensure the function and *** Due to various factors such as the non-uniformity of the processes and voltage drop,the response of each pixel in the silicon pixel module is not identical *** response difference of pixels can be minimized by the threshold *** system is developed for the quality test and calibration of the silicon pixel *** The system consists of a mother board,a control board and a data acquisition(DAQ)*** mother board provides necessary resources including power supplies and the fanout of calibration ***,it can be used to test the connectivity by monitoring the power *** control board reads data out and provides the clock,trigger and configuration data for the silicon pixel *** DAQ system sends the control commands and receives the readout data through an Ethernet *** Compared with the previous readout system,this designed system has a lower noise level and better scanning curves making the calibration more *** it has been successfully applied to the comparison experiments of the through silicon via and wire-bonding silicon pixel *** The results show that this test system can be used to the quality test and calibration of the silicon pixel *** addition,the system can be adapted to the measurement of different pixel array detector modules.

关键词： Hybrid silicon pixel module Test and calibration Power management Through silicon via and wire-bonding HEPS

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Reliability studies of the custom-designed front-end and ADC chips used for JUNO large photomultipliers electronics

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Radiation Detection Technology and Methods 2024年第2期8卷 1239-1245页

作者： Pei-ran Ye Xiong-bo Yan Zhe Ning Jun Hu Wei Wei xiao-shan jiang Ru-yi Jin Yun-hua Sun Qing-pei Hu Yu-sheng Wang Mu-jin Li Institute of High Energy Physics Chinese Academy of SciencesBeijing100049China State Key Laboratory of Particle Detection and Electronics Beijing100049China University of Chinese Academy of Sciences Beijing100049China Academy of Mathematics and System Science Chinese Academy of SciencesBeijing100190China

Objective The jiangmen Underground Neutrino Observatory,which is currently being constructed in South China,will be a cutting-edge liquid scintillator detector for neutrino physics in the coming *** read-out electronics will be installed in close proximity to the large photomultipliers and directly inside the water pool surrounding the *** installed,these electronics will not be accessible for repair or replacement;therefore,ensuring their reliability is of utmost importance.A crucial aspect of this reliability analysis involves evaluating the failure rate of custom-designed analog-to-digital converter and front-end chips used in underwater read-out *** The Arrhenius model shall be utilized to compute the reliability failure rate *** ageing,the ambient temperature of the setup system was set at 115℃.The high-gain and low-gain output channels were chosen as references for detecting failures in the tested sample for front-end chips of jiangmen Underground Neutrino Observatory,while for analog-to-digital converters,effective number of bits are considered as reference *** After ageing,all chips were *** ADC and FEC tests revealed no *** a result,the upper limit for the failure rate of front-end chips is 0.43 failures in time,and the upper limit for analog-to-digital converters is 0.42 failures in time at 30°*** The reliability test result shows that custom-designed chips can be used in underwater read-out electronics of jiangmen Underground Neutrino Observatory.

关键词： Reliability Failure rate ADC FEC

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A Novel Location detection Service Model in Cellular Networks

A Novel Location detection Service Model in Cellular Network...

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2010 IEEE 2nd Symposium on Web Society

作者： Qiu Lin,Song Meina,xiao shan,jiang Haiou Beijing University of Posts and Telecommunications

＜正＞In this paper,we present a novel location detection service model on applying data correlation methods to locate mobile stations within a cellular *** the proposed location detection algorithm,the mobile stations’ signal strength values which obtained from the periodic Mobile Station measurement reports from Abis interface is used to calculate the position of Mobile Station（MS）.The location detection service model is designed based on the correlation of MS measurement reports data sets and Base Station（BTS） related data sets and hence requires no additional hardware *** location detection platform running results were presented and compared with the real world road tests,which indicate that this novel location detection service system can provide effective information on Mobile Station’s position.

关键词： Location Detection Service Model Location detection Algorithm Database Correlation

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