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NEW APPROACH TO EMULATE SEU FAULTS ON SRAM BASED FPGAS

Journal of Electronics(China) 2014年第1期31卷 68-77页

作者： reza omidi gosheblagh Karim Mohammadi Department of Electrical Engineering Iran University of Science and Technology (IUST)

Field Programmable Gate Arrays(FPGAs)offer high capability in implementing of complex systems,and currently are an attractive solution for space system ***,FPGAs are susceptible to radiation induced Single-Event Upsets(SEUs).To insure reliable operation of FPGA based systems in a harsh radiation environment,various SEU mitigation techniques have been *** this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in *** proposed approach combines the fault injection controller with the host FPGA,and therefore the hardware complexity is *** of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host *** results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.

关键词： Field Programmable Gate Arrays(FPGAs) Single-Event Upset(SEU) fault injection Soft-core Space radiation effects

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HYBRID REDUNDANCY APPROACH TO INCREASE THE RELIABILITY OF FPGA BASED SPEED CONTROLLER CORE FOR HIGH SPEED TRAIN

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Journal of Electronics(China) 2014年第3期31卷 256-266页

作者： Omid Akbari Galashi Karim Mohammadi reza omidi gosheblagh Department of Electrical Engineering Iran University of Science and Technology (IUST)NarmakTehran 16846-13114 Iran

With the progress of the railway technology, the railway transportation is becoming more efficient, intelligent and faster. High speed trains, as a major part of the railway transportation, are engaged with passenger's safety, and therefore the reliability issue is very important in such vital systems. In this paper, a dependable speed controller core based on FPGA has been developed for high speed trains. To improve the reliability and mitigate single upset faults on basic speed controller, this paper proposes a new effective method which is based on hardware redundancy. In the proposed Hybrid Dual Duplex Redundancy(HDDR) method, the original controller is quadruplicated and correct values are voted through the comparator and error detection unit. We have analyzed the proposed system with Reliability, Availability, Mean time to failure and Security(RAMS) theory in order to evaluate the effectiveness of proposed scheme. Theoretical analysis shows that the Mean Time To Failure(MTTF) of the proposed system is 2.5 times better than the traditional Triple Modular Redundancy(TMR). Furthermore, the fault injection experimental results reveal that the capability of tolerating Single Event Upsets(SEUs) in the proposed method increases up to 7.5 times with respect to a regular speed controller.

关键词： Field Programmable Gate Arrays (FPGAs) Hybrid Dual Duplex Redundancy (HDDR) Fault tolerant system Reliability High speed railway

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