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Science China(Information Sciences) 2016年第4期59卷 152-159页

作者： Pengcheng HUANG Shuming chen jianjun chen College of Computer National University of Defense Technology National Laboratory for Parallel and Distributed Processing National University of Defense Technology

Single event upset (SEU) is one of the most important origins of soft errors in aerospace *** technology scales down persistently, charge sharing is playing a more and more significant effect on SEU of flip-flop. Charge sharing can often bring about multi-node charge collection in storage nodes and non-storage nodes in a flip-flop. In this paper, multi-node charge collection in flip-flop data input and flip-flop clock signal is investigated by 3D TCAD mixed-mode simulations, and the simulate results indicate that single event double transient (SEDT) in flip-flop data input and flip-flop clock signal can also cause a SEU in flip-flop. This novel mechanism is called the SEDT-induced SEU, and it is also verified by heavy-ion experiment in 65 nm twin-well process. The simulation results also indicate that this mechanism is closely related with the well-structure,and the triple-well structure is more effective to increase the SEU threshold of this mechanism than twin-well structure.

关键词： single event upset (SEU) single event double transient (SEDT) SEDT-induced SEU parasitic bipolar effect (PBE) charge sharing

Characterization of single-event multiple cell upsets in a custom SRAM in a 65 nm triple-well CMOS technology

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Science China(Technological Sciences) 2015年第10期58卷 1726-1730页

作者： chen HaiYan chen jianjun YAO Long School of Computer National University of Defense Technology

In this paper, the characterization of single event multiple cell upsets(MCUs) in a custom SRAM is performed in a 65 nm triple-well CMOS technology, and O(linear energy transfer(LET) = 3.1 Me V cm2/mg), Ti(LET = 22.2 Me V cm2/mg) and Ge(LET = 37.4 Me V cm2/mg) particles are employed. The experimental results show that the percentage of MCU events in total upset events is 71.11%, 83.47% and 85.53% at O, Ti and Ge exposures. Moreover, due to the vertical well isolation layout, 100%(O), 100%(Ti) and 98.11%(Ge) MCU cluster just present at one or two adjacent columns, but there are still 4 cell upsets in one MCU cluster appearing on the same word wire. The characterization indicates that MCUs have become the main source of soft errors in SRAM, and even though combining the storage array interleaving distance(ID) scheme with the error detection and correction(EDAC) technique, the MCUs cannot be completely eliminated, new radiation hardened by design techniques still need to be further studied.

关键词： multiple cell upsets (MCUs) static random access memories (SRAM) vertical well isolation radiation hardened by de-sign

Simulation analysis of heavy-ion-induced single-event response for nanoscale bulk-Si FinFETs and conventional planar devices

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Science China(Technological Sciences) 2017年第3期60卷 459-466页

作者： YU JunTing chen ShuMing chen jianjun HUANG Pengcheng College of Computer National University of Defense Technology Changsha 410073 China National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

FinFET technologies are becoming the mainstream process as technology scales *** on 28-nm bulk-Si FinFETs and

关键词： charge collection bipolar amplification reversed bipolar effect single-event effect(SEE) single-event transient(SET) FinFET planar device

Experimental characterization of the bipolar effect on P-hit single-event transients in 65 nm twin-well and triple-well CMOS technologies

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Science China(Technological Sciences) 2016年第3期59卷 488-493页

作者： chen jianjun LIANG Bin CHI YaQing School of Computer National University of Defense Technology

Single-event charge collection is controlled by drift, diffusion and the bipolar effect. Previous work has established that the bipolar effect is significant in the p-type metal-oxide-semiconductor field-effect transistor(PMOS) in 90 nm technology and above. However, the consequences of the bipolar effect on P-hit single-event transients have still not completely been characterized in 65 nm technology. In this paper, characterization of the consequences of the bipolar effect on P-hit single-event transients is performed by heavy ion experiments in both 65 nm twin-well and triple-well complementary metal-oxide-semiconductor(CMOS) technologies. Two inverter chains with clever layout structures are explored for the characterization. Ge(linear energy transfer(LET) = 37.4 Me V cm^2/mg) and Ti(LET = 22.2 Me V cm^2/mg) particles are also employed. The experimental results show that with Ge(Ti) exposure, the average pulse reduction is 49 ps(45 ps) in triple-well CMOS technology and 42 ps(32 ps) in twin-well CMOS technology when the bipolar effect is efficiently mitigated. This characterization will provide an important reference for radiation hardening integrated circuit design.

关键词： single event transient (SET) bipolar effect quantitative characterization

Cost-effective SET-tolerant clock distribution network design by mitigating single event transient propagation

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Science China(Information Sciences) 2017年第10期60卷 261-263页

作者： Peipei HAO Shuming chen Pengcheng HUANG jianjun chen Bin LIANG Institute of Microelectronics College of ComputerNational University of Defense Technology National Laboratory for Paralleling and Distributed Processing College of ComputerNational University of Defense Technology

It has been shown that clock distribution networks(CDNs)are becoming increasingly vulnerable to transient faults known as single event transients(SETs),owing to technology scaling[1].In the deep submicron regime,CDNs ... 详细信息

关键词： SET In

3-D TCAD simulation study of the single event effect on 25 nm raised source-drain FinFET

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Science China(Technological Sciences) 2012年第6期55卷 1576-1580页

作者： QIN JunRui chen ShuMing chen jianjun School of Computer Science National University of Defense TechnologyChangsha 410073China

Using Technology Computer-Aided Design(TCAD) 3-D simulation,the single event effect(SEE) of 25 nm raised source-drain FinFET is *** on the calibrated 3-D models by process simulation,it is found that the amount of charge collected increases linearly as the linear energy transfer(LET) increases for both n-type and p-type FinFET hits,but the single event transient(SET) pulse width is not linear with the incidence LET and the increasing rate will gradually reduce as the LET *** impacts of wafer thickness on the charge collection are also analyzed,and it is shown that a larger thickness can bring about stronger charge *** reducing the wafer thickness could mitigate the SET effect for FinFET technology.

关键词： FinFET single event effect single event transient charge collection

Novel N-hit single event transient mitigation technique via open guard transistor in 65 nm bulk CMOS process

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Science China(Technological Sciences) 2013年第2期56卷 271-279页

作者： HUANG Pengcheng chen ShuMing chen jianjun LIU BiWei School of Computer Science National University of Defense Technology

In this paper,we proposed a new n-channel MOS single event transient(SET) mitigation technique,which is called the open guard transistor(OGT) *** hardening scheme is compared with several classical n-channel MOS hardening structures through 3-D TCAD *** results show that this scheme presents about 35% improvements over the unhardened scheme for mitigating the SET pulse,and its upgrade,the 2-fringe scheme,takes on even more than 50% improvements over the unhardened *** makes significant sense for the semi-conductor device reliability.

关键词： single event transient (SET) open guard transistor (OGT) charge collection hardening efficiency.

The off-state gate isolation technique to improve ASET tolerance in differential analog design

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Science China(Technological Sciences) 2013年第10期56卷 2599-2605页

作者： HU ChunMei chen ShuMing chen jianjun QIN JunRui College of Computer National University of Defense Technology

A novel off-state gate RHBD technique to mitigate the single-event transient(SET)in the differential data path of analog circuit is demonstrated in this *** results present that this off-state gate technique could exploit charge sharing in differential circuits and reduce differential mode voltage perturbation *** is indicated that this technique is more effective to mitigate SET than the differential charge cancellation(DCC)technique with less penalty.

关键词： charge sharing ASET off-state gate layout mitigation technique

Single event transient pulse attenuation effect in three-transistor inverter chain

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Science China(Technological Sciences) 2012年第4期55卷 867-871页

作者： chen jianjun chen ShuMing LIANG Bin LIU FanYu School of Computer National University of Defense TechnologyChangsha 410073China

In this paper, compared with two-transistor (2T) inverter chain, the production and propagation of P-hit single event transient (SET) in three-transistor (3T) inverter chain is studied in depth based on three-dimensional numerical simulations in a 90 nm bulk complementary metal oxide semiconductor (CMOS) technology. The pulse attenuation effect is found in 3T inverter chain, and the pulse can not completely propagate through the inverter chain as LET increases. The discovery will provide a new insight into SET hardened design, the 3T inverter layout structure (or similar layout structures) will be a better method in integrated circuits (ICs) design in radiation environment.

关键词： single event transient (SET) pulse attenuation effect parasitic bipolar amplification effect

Dependency of well-contact density on MCUs in 65-nm bulk CMOS SRAM

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Science China(Information Sciences) 2019年第6期62卷 171-173页

作者： cheng XIE Yueyue chen jianjun chen Jizuo ZHANG College of Computer National University of Defense Technology

Dear editor,In custom static random access memory (SRAM)cell, radiation-induced single bit upsets (SBUs)are considered as the main cause of soft error [1].Advanced technologies and scaling down of feature sizes have m... 详细信息

关键词： Dependency of well-contact density on MCUs in 65-nm bulk CMOS SRAM MCU