Characterization of single-event multiple cell upsets in a custom SRAM in a 65 nm triple-well CMOS technology

作     者：CHEN HaiYan CHEN JianJun YAO Long 

作者机构：School of Computer National University of Defense Technology 

出 版 物：《Science China(Technological Sciences)》 (中国科学（技术科学英文版）)

年 卷 期：2015年第58卷第10期

页      面：1726-1730页

核心收录：

学科分类：07[理学] 08[工学] 070201[理学-理论物理] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 0702[理学-物理学] 

基　　金：supported by the National Natural Science Foundation of China(Grant No.61504169) the Preliminary Research Program of National University of Defense Technology of China(Grant No.0100066314001) 

主　　题：multiple cell upsets (MCUs) static random access memories (SRAM) vertical well isolation radiation hardened by de-sign 

摘      要：In this paper, the characterization of single event multiple cell upsets(MCUs) in a custom SRAM is performed in a 65 nm triple-well CMOS technology, and O(linear energy transfer(LET) = 3.1 Me V cm2/mg), Ti(LET = 22.2 Me V cm2/mg) and Ge(LET = 37.4 Me V cm2/mg) particles are employed. The experimental results show that the percentage of MCU events in total upset events is 71.11%, 83.47% and 85.53% at O, Ti and Ge exposures. Moreover, due to the vertical well isolation layout, 100%(O), 100%(Ti) and 98.11%(Ge) MCU cluster just present at one or two adjacent columns, but there are still 4 cell upsets in one MCU cluster appearing on the same word wire. The characterization indicates that MCUs have become the main source of soft errors in SRAM, and even though combining the storage array interleaving distance(ID) scheme with the error detection and correction(EDAC) technique, the MCUs cannot be completely eliminated, new radiation hardened by design techniques still need to be further studied.