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New Model and Algorithm for Hardware/Software Partitioning

Journal of Computer Science & Technology 2008年第4期23卷 644-651页

作者：武继刚 thambipillai srikanthan 邹广伟 Centre for High Performance Embedded Systems School of Computer EngineeringNanyang Technological University

This paper focuses on the algorithmic aspects for the hardware/software （HW/SW） partitioning which searches a reasonable composition of hardware and software components which not only satisfies the constraint of hardware area but also optimizes the execution time. The computational model is extended so that all possible types of communications can be taken into account for the HW/SW partitioning. Also, a new dynamic programming algorithm is proposed on the basis of the computational model, in which source data, rather than speedup in previous work, of basic scheduling blocks are directly utilized to calculate the optimal solution. The proposed algorithm runs in O（n·A） for n code fragments and the available hardware area A. Simulation results show that the proposed algorithm solves the HW/SW partitioning without increase in running time, compared with the algorithm cited in the literature.

关键词： algorithm hardware/software partitioning dynamic programming complexity

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Power Efficient Sub-Array in Reconfigurable VLSI Meshes

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Journal of Computer Science & Technology 2005年第5期20卷 647-653页

作者： Ji-Gang Wu thambipillai srikanthan Centre for High Performance Embedded Systems School of Computer Engineering Nanyang Technological University Singapore 639798

Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.

关键词： degradable VLSI mesh reconfiguration heuristic algorithm fault-tolerance NP-complete

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CADSE： communication aware design space exploration for efficient run-time MPSoC management

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Frontiers of Computer Science 2013年第3期7卷 416-430页

作者： Amit Kumar SINGH Akash KUMAR Jigang WU thambipillai srikanthan Department of Electrical and Computer Engineering National University of Singapore Singapore 119077 Singapore School of Computer Science and Software Engineering Tianjin Polytechnic University Tianjin 300160 China School of Computer Engineering Nanyang Technological University Singapore 639798 Singapore

Real-time multi-media applications are increasingly mapped on modern embedded systems based on multiprocessor systems-on-chip （MPSoC）. Tasks of the applications need to be mapped on the MPSoC resources efficiently in order to satisity their performance constraints. Exploring all the possible mappings, i.e., tasks to resources combinations exhaustively may take days or weeks. Additionally, the exploration is performed at design-time, which cannot handle dynamism in applications and resources＇ status. A runtime mapping technique can cater for the dynamism but cannot guarantee for strict timing deadlines due to large computations involved at run-time. Thus, an approach performing feasible compute intensive exploration at design-time and using the explored results at run-time is required. This paper presents a solution in the same direction. Communicationaware design space exploration （CADSE） techniques have been proposed to explore different mapping options to be selected at run-time subject to desired performance and available MPSoC resources. Experiments show that the proposed techniques for exploration are faster over an exhaustive exploration and provides almost the same quality of results.

关键词： multiprocessor systems-on-chip design space exploration run-time mapping synchronous dataflow graphs throughput

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