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LSB page refresh based retention error recovery scheme for MLC NAND Flash

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Science China(Information Sciences) 2016年第4期59卷 121-131页

作者： Haozhi MA Lifang LIU liyang pan Jun XU Institute of Microelectronics Tsinghua University Tsinghua National Laboratory for Information Science and Technology

NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell(MLC) technology. High retention error rate in highly program/erase(P/E) cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit(LSB) page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Compared with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.

关键词： NAND flash reliability retention refresh data error recovery

A 1G-cell floating-gate NOR flash memory in 65 nm technology with 100 ns random access time

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Science China(Information Sciences) 2015年第4期58卷 158-165页

作者： LIU LiFang WU Dong LIU XueMei HUO ZongLiang LIU Ming pan liyang Institute of Microelectronics University of Tsinghua Tsinghua National Laboratory for Information Science and Technology Laboratory of Nano-Fabrication and Novel Devices Integrated Technology Institute of MicroelectronicsChinese Academy of Sciences

A 1G-cell NOR flash memory chip has been designed and fabricated successfully with 65 nm technology. To compromise the array efficiency and chip speed, the paper establishes an array model including parasitics of the whole array, and optimizes the sector structure as 512 wordlines(WLs) and 4096 bitlines(BLs).Furthermore, by adding other models of long and thin metal lines, we have analyzed the speed of critical circuit nodes. As a result, the agreement of WL delay between simulation and measurement verifies the accuracy of the array model and lines models. The test results indicate that the chip achieves random access time of 100 ns and page read time of 25 ns under 3.3 V voltage supply.

关键词： NOR flash memory giga-level 65 nm technology array efficiency high speed

Total ionizing radiation effects of 2-T SONOS for 130 nm/4 Mb NOR flash memory technology

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Science China(Information Sciences) 2014年第6期57卷 173-181页

作者： QIAO FengYing pan liyang YU Xiao MA HaoZhi WU Dong XU Jun Institute of Microelectronics Tsinghua University Tsinghua National Laboratory for Information Science and Technology

In this paper,we have studied the total ionizing dose(TID)radiation response up to 2 Mrad(Si)of silicon-oxide-nitride-oxide-silicon(SONOS)memory cells and memory circuits,fabricated in a 130 nm complimentary metal-oxide-semiconductor(CMOS)SONOS *** explored the threshold voltage(VT)degradation mechanism and found that the VT shifts of SONOS cells depend on the charge state;simply programming the cell to a higher VT cannot compensate for the radiation induced VT *** off-state current(Ioff)increase in the SONOS cell is also studied in this *** VT and Ioffdegradation would affect the memory *** data failures are mainly caused by VT shifts under irradiation,and program and erase failures are mainly caused by increased Ioff,which overloads the charge pumping *** varying the reference current,our 4 Mb NOR flash chip has the potential to survive a radiation dose of 1 Mrad(Si)in read mode.

关键词： silicon-oxide-nitride-oxide-silicon SONOS total ionizing dose TID flash memory radiation effects 130 nm

High Speed Sense Amplifier Circuit for Low-Voltage SONOS Memory Systems

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High Speed Sense Amplifier Circuit for Low-Voltage SONOS Mem...

A 65-nm 1-Gb NOR floating-gate flash memory with less than 50-ns access time

2005 6th International Conference on ASIC

作者： Guangjun yang liyang pan Dong wu Jun zhu Institute of Microelectronics Tsinghua University

ISBN: (纸本)0780392108;9780780392106;0780392108;9780780392106

＜正＞In this paper,a new high speed sense amplifier with high voltage driven load and inner multiple power supplies techniques for 0.9V power supply embedded SONOS memory systems is *** voltage driven load technique is introduced to increase the voltage swing on the data-line and to improve the sensing *** multiple power supplies technique is adopted to improve sensing speed by increasing the input range and the comparing speed of comparator under low power *** sense amplifier was implemented in CMOS compatible embedded SONOS *** results show that the sensing delay is 1.7ns under the typical condition with 0.9V power supply.

关键词： SONOS devices Power supplies Threshold voltage High power amplifiers Delay Circuit noise Decoding Charge pumps Circuit topology Mirrors

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Chinese Science Bulletin 2014年第29期59卷 3935-3942页

作者： Yu Wang Zongliang Huo Huamin Cao Ting Li Jing Liu liyang pan Xing Zhang Yun Yang Shenfeng Qiu Hanming Wu Ming Liu Laboratory of Nano-fabrication and Novel Device Integration Institute of MicroelectronicsChinese Academy of Sciences Institute of Microelectronics Tsinghua University Institute of Microelectronics Peking University Semiconductor Manufacturing International Corporation

This paper presents a 65-nm 1-Gb NOR-type floating-gate flash memory,in which the cell device and chip circuit are developed and *** order to solve the speed problem of giga-level NOR flash in the deep submicron process,the models of long bit-line and word-line are first given,by which the capacitive and resistive loads could be *** on that,the read path and key modules are optimized to enhance the chip access property and *** the measurement results,the flash memory cell presents good endurance and retention properties,and the macro is operated with 1-ls/byte program speed and less than 50-ns read time under 3.3 V supply.

关键词： NOR闪存访问时间 GB 浮栅 ns 深亚微米工艺芯片电路速度问题

Discussion on the CHE Programming Characteristics with the Scaling Down of Charge Trapping Flash Memory

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Discussion on the CHE Programming Characteristics with the S...

基于CZ-BWT改进的LZW压缩算法在电力报文中的应用

2006 8th International Conference on Solid-State and Integrated Circuit Technology

作者： Lei Sun liyang pan Xian Luo Dong Wu Jun Zhu Institute of Microelectronics Tsinghua University

ISBN: (纸本)1424401607

＜正＞The scaling down issues in the charge trapping memory are investigated in this *** the sub-100 nm devices,the punch-through problem,as well as high program voltage and electrical field limitation are studied by device simulation and *** found CHE program mechanism will eventually meet certain limitation in the future short channel devices. Furthermore,program induced charge distribution is extracted by a charge pumping method,and the related problems to the multi-bit application is discussed.

关键词： CHARGE TRAPPING Scale formation Dental Scaling Scaling Charge pumps flash memories Northern Ireland FLUFF Debates Programming induced charge CHARGE DISTRIBUTION

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计算机集成制造系统 2024年第8期30卷 2947-2953页

作者：周航潘小辉孙佳炜腾力阳江结林国网南京供电公司江苏南京210019 南京信息工程大学软件学院江苏南京210044

随着电网远动信息数据量日益剧增,对有限的硬件存储和网络带宽带来严峻考验。通过对报文数据的无损压缩研究以缓解硬件设备压力,确保数据解压后能无损还原出压缩之前的数据显得尤为重要。针对IEC60870-5-104报文特有结构及LZW(Lempel-Zi... 详细信息

随着电网远动信息数据量日益剧增,对有限的硬件存储和网络带宽带来严峻考验。通过对报文数据的无损压缩研究以缓解硬件设备压力,确保数据解压后能无损还原出压缩之前的数据显得尤为重要。针对IEC60870-5-104报文特有结构及LZW(Lempel-Ziv-Welch)的特点,提出基于截断CZ-BWT(Burrows-Wheeler transform)改进的LZW报文压缩算法。首先对输入的IEC60870-5-104报文进行CZ-BWT转换作为预处理,增大报文内容的相关性;其次用LZW算法对转换后的数据进行压缩操作。实验结果表明,基于CZ-BWT改进的LZW算法的压缩率优于传统LZW算法。此外,在压缩和解压速度方面,相比于大部分的压缩算法而言,具有一定优势。

关键词：数据压缩 LZW算法远动信息规约无损压缩

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抗磷脂抗体与狼疮性肾炎的相关性研究

中国免疫学杂志 2022年第24期38卷 3035-3038,3043页

作者：于淼琛姜艳梅潘立阳王贞段梦夕大连医科大学附属第一医院检验科大连116011 大连市疾病预防控制中心传染病地方病防制所大连116011

目的:探讨抗心磷脂抗体(aCL)IgG、IgM、抗β2-糖蛋白1(β2-GP1)抗体IgG、IgM及其他指标与狼疮性肾炎(LN)和系统性红斑狼疮(SLE)的相关性。方法:检测LN及无肾脏累及的SLE患者aCL(IgG、IgM)、抗β2-GP1抗体(IgG、IgM)、C3、C4、抗ds-DNA... 详细信息

目的:探讨抗心磷脂抗体(aCL)IgG、IgM、抗β2-糖蛋白1(β2-GP1)抗体IgG、IgM及其他指标与狼疮性肾炎(LN)和系统性红斑狼疮(SLE)的相关性。方法:检测LN及无肾脏累及的SLE患者aCL(IgG、IgM)、抗β2-GP1抗体(IgG、IgM)、C3、C4、抗ds-DNA抗体、肌酐、尿蛋白等指标,判断其与LN和SLE疾病相关程度。结果:LN组与无肾脏累及的SLE组患者肌酐、尿蛋白定量和IgG型抗β2-GP1差异有统计学意义(P=0.005、P=0.000、P=0.003);IgG、IgM型aCL、IgM型抗β2-GP1抗体阳性率、抗ds-DNA抗体、C3、C4水平差异无统计学意义(P>0.05)。进一步对SLEDAI评分分组,LN组IgG型aCL(P=0.048,r=0.318)与LN疾病活动呈弱正相关,而C3(P=0.005,r=-0.439)与LN疾病活动呈中等程度的负相关;LN组IgM型aCL、IgG、IgM型抗β2-GP1抗体浓度、尿蛋白定量、抗ds-DNA抗体、C4、肌酐水平与疾病活动程度无相关性(P>0.05)。无肾脏累及的SLE组以上各项指标与疾病活动程度均无相关性(P>0.05)。结论:LN患者血清中C3、IgG型aCL与疾病进展相关,可作为LN疾病诊治过程中的辅助诊断指标。

关键词：狼疮性肾炎系统性红斑狼疮抗磷脂抗体相关性

一种新型大驱动、低功耗和高精度的电荷泵电路

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固体电子学研究与进展 2005年第3期25卷 379-384页

作者：伍冬潘立阳段志刚朱钧清华大学微电子学研究所北京100084

提出一种适用于NOR结构快闪存储器应用的,具有大驱动能力、低功耗和高精度特性的电荷泵系统。它通过对八个子电荷泵的并联来提高电荷泵的驱动能力,并采用电容分离法来动态地自洽改变每个子电荷泵的驱动能力,仿真结果表明,在擦除模式、... 详细信息

提出一种适用于NOR结构快闪存储器应用的,具有大驱动能力、低功耗和高精度特性的电荷泵系统。它通过对八个子电荷泵的并联来提高电荷泵的驱动能力,并采用电容分离法来动态地自洽改变每个子电荷泵的驱动能力,仿真结果表明,在擦除模式、一位编程模式和八位编程模式工作下,其瞬态平均电流分别约为2.5mA、4 mA和12 mA,电荷泵的输出高压精度可达±2.3%以下,达到了节省功耗和提高输出高压精度的目的。

关键词： NOR结构快闪存储器电荷泵驱动能力