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FPGA Implementation of 5G NR Primary and Secondary Synchronization

Computers, Materials & Continua 2022年第10期73卷 1585-1600页

作者： Aytha Ramesh kumar k.lal kishore Department of ECE VNR Vignana Jyothi Institute of Engineering&TechnologyHyderabad500090India JNTUA Former Vice ChancellorIndia

The 5G communication systems are widely established for highspeed data processing to meet users *** 5G New Radio(NR)communications comprise a network of ultra-low latency,high processing speeds,high throughput and rapid synchronization with a time frame of 10 *** between User Equipment(UE)and 5G base station known as gNB is a fundamental procedure in a cellular system and it is performed by a synchronization *** 5G NR system,Primary Synchronization Signal(PSS)and Secondary Synchronization Signal(SSS)are used to detect the best serving base station with the help of a cell search *** paper aims to determine the Physical Cell Identity(PCI)by using primary synchronization and secondary synchronization *** PSS and SSS detection for finding PCI is implemented on Zynq-7000 series Field Programmable Gate Arrays(FPGA)*** are reconfigurable devices and easy to design complex circuits at high *** proposed architecture employs Primary Synchronization Signal(PSS)and Secondary Synchronization Signal(SSS)detection aims with high speed and low power *** synchronization blocks have been designed and the synthesized design block is implemented on the Zynq-7000 series Zed board with a maximum operating clock frequency of 1 GHz.

关键词： 5G new radio FPGA physical cell identity primary and secondary synchronization

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Hierarchical Matched Filter Implementation on FPGA for WCDMA Systems

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通讯和计算机（中英文版） 2011年第8期8卷 686-692页

作者： Aytha.Ramesh kumar B.L. Malleswari k.lal kishore Vignana Jyothi Institute of Engineering and Technology JNT University Hyderabad 500042 India G. Narayanamma Institute of Technology and Science JNT University Hyderabad 500008 India Jawaharlal Nehru Technological University Hyderabad 500090 India

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Optimizing the Stage Resolution of a 10-Bit, 50 Ms/Sec Pipelined A/D Converter &Its Impact on Speed, Power, Area, and Linearity

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Circuits and Systems 2012年第2期3卷 166-175页

作者： Perala Prasad Rao kondepudi lal kishore Department of Electronics and Communication Engineering Jawaharlal Nehru Technological University Hyderabad India

At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.

关键词： Switched Capacitor Sample and Hold Circuit 1.5 Bits/Stage Linearity Power Redundancy Folded Cascode Op-Amp

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