FPGA Implementation of 5G NR Primary and Secondary Synchronization

作     者：Aytha Ramesh Kumar K.Lal Kishore 

作者机构：Department of ECEVNR Vignana Jyothi Institute of Engineering&TechnologyHyderabad500090India JNTUAFormer Vice ChancellorIndia 

出 版 物：《Computers, Materials & Continua》 (计算机、材料和连续体（英文）)

年 卷 期：2022年第73卷第10期

页      面：1585-1600页

核心收录：

学科分类：0831[工学-生物医学工程（可授工学、理学、医学学位）] 0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0805[工学-材料科学与工程（可授工学、理学学位）] 0701[理学-数学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 0801[工学-力学（可授工学、理学学位）] 

主　　题：5G new radio FPGA physical cell identity primary and secondary synchronization 

摘      要：The 5G communication systems are widely established for highspeed data processing to meet users *** 5G New Radio(NR)communications comprise a network of ultra-low latency,high processing speeds,high throughput and rapid synchronization with a time frame of 10 *** between User Equipment(UE)and 5G base station known as gNB is a fundamental procedure in a cellular system and it is performed by a synchronization *** 5G NR system,Primary Synchronization Signal(PSS)and Secondary Synchronization Signal(SSS)are used to detect the best serving base station with the help of a cell search *** paper aims to determine the Physical Cell Identity(PCI)by using primary synchronization and secondary synchronization *** PSS and SSS detection for finding PCI is implemented on Zynq-7000 series Field Programmable Gate Arrays(FPGA)*** are reconfigurable devices and easy to design complex circuits at high *** proposed architecture employs Primary Synchronization Signal(PSS)and Secondary Synchronization Signal(SSS)detection aims with high speed and low power *** synchronization blocks have been designed and the synthesized design block is implemented on the Zynq-7000 series Zed board with a maximum operating clock frequency of 1 GHz.