检索结果-南通市图书馆

A novel method of optimizing latch comparators

在线全文

学校读者我要写书评

暂无评论

High Technology Letters 2019年第3期25卷 255-261页

作者：郑浩 fan xiangning Institute of RF&OE-ICs School of Information Science and EngineeringSoutheast University

A new method of improving speed of latch-type comparators with preamplifier is presented. It investigates the relationship of current and transistor scales which affect delay time(tp) in latch. It applies a mathematical model to optimize latch design. A figure of merit indicates that ratio Ipmos/Inmos is 0.25 in latch leading to optimal delay time. In order to suppress offset of latch, the cross-coupled loading, adopted in telescope preamplifier, which enhances the gain, is well analyzed and designed. The chip is fabricated in 0.18 μm CMOS technology. The delay time of latch comparator is less than 400 ps @500 MHz. The offset of comparator is estimated through Monte Carlo simulation. And power consumption is only 144 W under 1.8 V power supply. Results of on wafer testing are presented at the end of the paper. The chip occupies an area of 0.66×0.55 mm^2 and drains current of 80 μA.

关键词： cross-couple latch offset telescope amplifier with cross-couple loading delay time

A wideband LC-VCO for MMMS applications

在线全文

学校读者我要写书评

暂无评论

High Technology Letters 2020年第1期26卷 1-7页

作者：廖一龙 fan xiangning Institute of RF-&OE-ICs School of Information Science and EngineeringSoutheast UniversityNanjing 210096P.R.China

A fully integrated wideband voltage-controlled-oscillator(VCO) based on current-reused topology is presented. The overall scheme contains two sub-VCOs, which are controlled by a switch to cover a wide output frequency range. Fabricated in TSMC 65 nm CMOS technology, the measured output frequency of the VCO ranges from 3.991 GHz to 9.713 GHz,achieving a tuning range of 83.5%. And the worst and best phase noise at 1 MHz offset are-93.09 dBc/Hz and-111.97 dBc/Hz, respectively. With a 1.2 V supply voltage, the VCO core consumes a current of 3.7-5.1 mA across the entire frequency range. The chip area is 0.51 mm^2, including the pads. Moreover, the proposed VCO provides a figure-of-merit-with-tuning-range(FOM_T) of-191 dBc/Hz to-197 dBc/Hz.

关键词： current-reuse phase noise voltage-controlled-oscillator(VCO) wideband

A tunable passive mixer for SAW-less front-end with reconfigurable voltage conversion gain and intermediate frequency bandwidth

在线全文

学校读者我要写书评

暂无评论

High Technology Letters 2018年第1期24卷 10-18页

作者：陶健 fan xiangning zhao yuan Institute of RF&OE-ICs School of Information Science and Engineering Southeast University Nanjing 210096 P. R. China

An adjustable mixer for surface acoustic wave( SAW)-less radio frequency( RF) front-end is presented in this paper. Through changing the bias voltage,the presented mixer with reconfigurable voltage conversion gain( VCG) is suitable for multi-mode multi-standard( MMMS) applications. An equivalent local oscillator( LO) frequency-tunable high-Q band-pass filter( BPF) at low noise amplifier( LNA) output is used to reject the out-of-band interference signals. Base-band( BB) capacitor of the mixer is variable to obtain 15 kinds of intermediate frequency( IF) bandwidth( BW). The proposed passive mixer with LNA is implemented in TSMC 0. 18μm RF CMOS process and operates from 0. 5 to 2. 5 GHz with measured maximum out-of-band rejection larger than 40 d B. The measured VCG of the front-end can be changed from 5 to 17 d B; the maximum input intercept point( IIP3) is0 d Bm and the minimum noise figure( NF) is 3. 7 d B. The chip occupies an area of 0. 44 mm^2 including pads.

关键词： reconfigurable radio frequency (RF) front-end multi-mode multi-standard( MMMS) high-Q band-pass filter ( BPF) cross-coupled common gate low noise amplifier ( CC-CGLNA) CMOS

A new digital transmitter based on delta sigma modulator with bus-splitting

在线全文

学校读者我要写书评

暂无评论

High Technology Letters 2018年第2期24卷 117-124页

作者：花再军 fan xiangning Liao Yilong Institute of RF-&OE-ICs School of Information Science and EngineeringSoutheast University

A new digital transmitter based on delta sigma modulator( DSM) with bus-splitting is presented in this paper. The second order low pass error-feedback delta sigma modulator( EF-DSM) is focused. The signal to noise ratio( SNR) of the EF-DSM is derived for different bus-splitting bits.Following the EF-DSM,a multi-bit digital up mixer is used for carrier frequency transform. In order to validate the theory of bus-splitting,two types of transmitters are implemented on FPGA for comparison,in which one is with non-bus-splitting and the other is with bus-splitting. The FPGA implemented transmitter with bus-splitting promotes the maximum operation speed by 39%,and reduces hardware consumptions more than 16%. Both single tone and orthogonal frequency division multiplexing( OFDM) signal source are used to evaluate the proposed transmitter.

关键词：公共汽车传输器三角洲 FPGA 频率变换操作速度频率分割通行证

A single-ended wideband reconfigurable receiver front-end for multi-mode multi-standard applications in 0.18μm CMOS

在线全文

学校读者我要写书评

暂无评论

High Technology Letters 2019年第1期25卷 1-7页

作者：陶健 fan xiangning Bao Kuan Institute of RF&OE-ICs School of Information Science and EngineeringSoutheast University

This paper presents a reconfigurable RF front-end for multi-mode multi-standard(MMMS) applications. The designed RF front-end is fabricated in 0.18 μm RF CMOS technology. The low noise characteristic is achieved by the noise canceling technique while the bandwidth is enhanced by gate inductive peaking technique. Measurement results show that, while the input frequency ranges from 100 MHz to 2.9 GHz, the proposed reconfigurable RF front-end achieves a controllable voltage conversion gain(VCG) from 18 dB to 39 dB. The measured maximum input third intercept point(IIP3) is-4.9 dBm and the minimum noise figure(NF) is 4.6 dB. The consumed current ranges from 16 mA to 26.5 mA from a 1.8 V supply voltage. The chip occupies an area of 1.17 mm^2 including pads.

关键词： reconfigurable multi-mode multi-standard (MMMS) receiver front-end gate inductive peaking noise canceling CMOS

Improved time-interleaved error feedback delta sigma modulator for digital transmitter application

在线全文

学校读者我要写书评

暂无评论

High Technology Letters 2018年第4期24卷 337-342页

作者：花再军 fan xiangning Liao Yilong Institute of RF-&OE-ICs School of Information Science and EngineeringSoutheast University

Time-interleaved structure can promote the equivalent processing speed of a digital signal processing system. An improved time-interleaved error feedback delta sigma modulator( TI-EF-DSM)for digital transmitter application is presented in this paper. Two TI-EF-DSMs are compared,one is a conventional directly implemented and the other is the improved. The processing speed of the proposed two-channel improved time-interleaved error feedback delta sigma modulator( ITI-EF-DSM) is higher than the conventional directly implemented TI-EF-DSM for shortened critical path. A digital transmitter based on the ITI-EF-DSM is implemented on field progrmmable gate array( FPGA). The long term evolution( LTE) signals with different bandwidths of 5 MHz,10 MHz and 20 MHz are used as the signal source to evaluate the transmitter. The achieved SNR is 41 dB for the 20 MHz LTE signal with the processing clock of only 184 MHz.

关键词： time-interleaved error feedback delta sigma modulator(EF-DSM) digital transmitter long term evolution(LTE)

A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator for MMMS applications

在线全文

学校读者我要写书评

暂无评论

High Technology Letters 2019年第3期25卷 231-238页

作者：廖一龙 fan xiangning Lin Zhi Shi Yongjian Hua Zaijun Institute of RF-&OE-ICs School of Information Science and EngineeringSoutheast University

A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator(NF-DSM) is presented. The phase switching circuit, realized by switching 8 signals generated by a divider-by-4 circuit, is adopted to reduce the frequency division step. The NF-DSM, which can obtain smooth output spectra, is proposed to generate the fractional part of the division ratio, moreover, the integer part of the division ratio is realized by a divider-by-2/3 circuit chain. Fabricated in TSMC 0.18 μm RF CMOS technology, the fractional frequency divider achieves a measured operation frequency from 0.5 GHz to 8 GHz. With a 1.8 V supply voltage, the maximum current consumption of the whole divider is 17.5 mA, and the chip area is 0.58 mm^2, including the pads.

关键词： delta-sigma modulator(DSM) divider-by-2/3 frequency divider phase switching

从“十一脏取决于胆”论治冠心病合并焦虑抑郁

在线全文

学校读者我要写书评

暂无评论

四川中医 2024年第5期42卷 34-37页

作者：丁帆王玉玲崔向宁北京中医药大学北京100029 中国中医科学院广安门医院心血管科北京100053

“十一脏取决于胆”首见于《素问》,强调胆在人体生命活动及临床治疗中的重要作用。冠心病具有病程长,易反复,需长期服药等特点,加之社会心理因素的影响,常易伴发焦虑抑郁。笔者在临床跟师过程中,发现导师从胆论治冠心病合并焦虑抑郁疗... 详细信息

“十一脏取决于胆”首见于《素问》,强调胆在人体生命活动及临床治疗中的重要作用。冠心病具有病程长,易反复,需长期服药等特点,加之社会心理因素的影响,常易伴发焦虑抑郁。笔者在临床跟师过程中,发现导师从胆论治冠心病合并焦虑抑郁疗效显著,“十一脏取决于胆”的理论在临床中得到验证。导师认为,一者,肝胆相合,共主疏泄,与气机疏泄密切相关;二者,胆寄情志,疏调气机,精神活动,决断于胆;三者,胆蕴相火,通行气血,君相安位,则气血和调;因此,本病的病机主要在于气机失调,相火妄动,导致脏腑经络失和,神机失用。基于此病机,本文结合案例介绍从胆论治冠心病合并焦虑抑郁之经验,以期为临床提供治疗思路。

关键词：冠心病合并焦虑抑郁从胆论治治法方药

在线全文

学校读者我要写书评

暂无评论

中医“通法”治疗双心疾病临床经验

辽宁中医杂志 2024年第3期51卷 21-23页

作者：沈子焕王玉玲焦林珂陈琛丁帆崔向宁北京中医药大学研究生院北京100029 中国中医科学院广安门医院北京100053

双心疾病是在患有心血管疾病的基础上合并精神心理疾病,目前西医尚无特效治疗方法。中医学认识到“滞”是双心疾病发生的病机关键,即郁瘀痰饮虚五端,虚实夹杂。人体气血津液、经络脏腑以“通”为安,失“通”则病,故治疗立足于“通法”... 详细信息

双心疾病是在患有心血管疾病的基础上合并精神心理疾病,目前西医尚无特效治疗方法。中医学认识到“滞”是双心疾病发生的病机关键,即郁瘀痰饮虚五端,虚实夹杂。人体气血津液、经络脏腑以“通”为安,失“通”则病,故治疗立足于“通法”灵活遣方用药,以疏肝理气、活血化瘀、温阳利水通其实滞;以滋阴养血、培元益气补虚通滞,调畅情志法贯穿始终,使气血得通,实邪得去,虚正得补,阴阳和合,疗效显著。

关键词：通法双心疾病中医名医经验