TCAD Application in Process Optimization to Reduce Source/Drain Junction Capacitance of PMOS Transistor in the Development of 65nm Low Leakage Technology
作者单位：Semiconductor Manufacturing International Corporation
会议名称：《2008 9th International Conference on Solid-State and Integrated-Circuit Technology》
会议日期：2008年
学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程（可授工学、理学学位）] 080502[工学-材料学]
摘 要：In this paper, technology computer aided design （TCAD） was applied to optimize the fabrication process to reduce the parasitic capacitance of PMOS transistor at the source/drian （S/D） junction （Cj） in developing the 65nm low leakage （65nmLL） technology. It was found that Cj can be effectively reduced by combining relative high-energy well implant and proper threshold voltage （Vt） implant method. Through measured data and TCAD simulation, this paper also demonstrates a doping compensation effect by tuning Vt and Halo implants with proper species, energy, and dosage, to achieve the Cj reduction.