Dopingless impact ionization MOS(DL-IMOS)—a remedy for complex process flow

作     者：Sangeeta Singh P.N.Kondekar 

作者机构：Department of Electronics and Communication EngineeringPDPM-Indian Institute of Information TechnologyDesign and Manufacturing (IIITDM) Jabalpur JabalpurMPIndia 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2015年第36卷第7期

页      面：50-58页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程（可授工学、理学学位）] 080502[工学-材料学] 0703[理学-化学] 0702[理学-物理学] 

主　　题：impact ionization MOSFET (IMOS) dopingless work-function engineering Debye length drain induced current enhancement (DICE) random dopant fluctuations (RDF) 

摘      要：We propose a unique approach for realizing dopingless impact ionization MOS （DL-IMOS） based on the charge plasma concept as a remedy for complex process flow. It uses work-function engineering of electrodes to form charge plasma as surrogate doping. This charge plasma induces a uniform p-region in the source side and an n-region in the drain side on intrinsic silicon film with a thickness less than the intrinsic Debye length. DL-IMOS offers a simple fabrication process flow as it avoids the need of ion implantation, photo masking and complicated thermal budget via annealing devices. The lower thermal budget is required for DL-IMOS fabrication enables its fabrication on single crystal silicon-on-glass substrate realized by wafer scale epitaxial transfer. It is highly immune to process variations, doping control issues and random dopant fluctuations, while retaining the inherent advantages of conventional IMOS. To epitomize the fabrication process flow for the proposed device a virtual fabrication flow is also proposed here. Extensive device simulation of the major device performance metrics such as subthreshold slope, threshold voltage, drain induced current enhancement, and breakdown voltage have been done for a wide range of electrodes work-function. To evaluate the potential applications of the proposed device at circuit level, its mixed mode simulations are also carried out.