Design Optimization of Pillar Bump Structure for Minimizing the Stress in Brittle Low K Dielectric Material Layer

作     者：Xin-Jiang Long Jin-Tang Shang Li Zhang Xin-Jiang Long;Jin-Tang Shang;Li Zhang

作者机构：Key Laboratory of MEMS of Ministry of EducationSoutheast UniversitySipailou 2#Nanjing 210096China Jiangyin Changdian Advanced Packaging Co.Ltd.No.275 Binjiang RdJiangyin 214400China 

出 版 物：《Acta Metallurgica Sinica(English Letters)》 (金属学报（英文版）)

年 卷 期：2020年第33卷第4期

页      面：583-594页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 0817[工学-化学工程与技术] 0806[工学-冶金工程] 08[工学] 0807[工学-动力工程及工程热物理] 0805[工学-材料科学与工程（可授工学、理学学位）] 0802[工学-机械工程] 0703[理学-化学] 0811[工学-控制科学与工程] 

基　　金：The technical support and discussion from Cheng Xu Kim-Hwee Tan and Zhi-Quan Liu are acknowledged 

主　　题：Cu pillar bump Flip chip Low K stress Undercut 

摘      要：Cu pillar bump offers a number of advantages for flip chip packaging,compared to the conventional solder ***,due to its rigidity structure,Cu pillar bump introduces a lot of stress to the chip,which causes the failure of packaging structures,especially for the advanced node devices which typically have brittle low K dielectric *** this paper,for the first time we propose two types of Cu pillar structures to reduce the *** first Cu pillar structure has bigger Cu dimensions at the *** other one is designed to add an additional Cu pad under the Cu pillar *** element analysis is used to study the stress of the both structures,and it is found that with the increase in pillar bump contact area over the chip surface,the stress decreases in both *** also indicate that the Cu pillar bump undercut induces higher stress,and thin Cu6 Snss intermetallic compound has less impact on the stress during flip chip mount *** study provides a novel way to improve the reliability by reducing the stress in the Cu pillar bump related packaging.