A 200 mV low leakage current subthreshold SRAM bitcell in a 130 nm CMOS process

作     者：柏娜 吕白涛 

作者机构：School of Information Science and EngineeringSoutheast University School of Electronics and Information EngineeringAnhui University 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2012年第33卷第6期

页      面：95-100页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：supported by the China State-Funded Study Abroad Program for High-Level Universities 

主　　题：subthreshold SRAM static noise margin leakage ultra low power 

摘      要：A low leakage current subthreshold SRAM in 130 nm CMOS technology is proposed for ultra low voltage（200 mV） *** all of the previous subthreshold works ignore the leakage current in both active and standby *** minimize leakage,a self-adaptive leakage cut off scheme is adopted in the proposed design without any extra dynamic energy dissipation or performance *** with buffering circuit and reconfigurable operation,the proposed design ensures both read and standby stability without deteriorating writability in the subthreshold *** to the referenced subthreshold SRAM bitcell,the proposed bitcell shows：（1） a better critical state noise margin,and（2） smaller leakage current in both active and standby modes. Measurement results show that the proposed SRAM functions well at a 200 mV supply voltage with 0.13μW power consumption at 138 kHz frequency.