Effect of gate length on the parameter degradation relations of PMOSFET under NBTI stress

作     者：曹艳荣 何文龙 曹成 杨毅 郑雪峰 马晓华 郝跃 

作者机构：School of Mechano-electric Engineering Xidian University Key Lab of Wide Band-Gap Semiconductor Materials and Devices School of Microelectronics Xidian University School of Technical Physics Xidian University 

出 版 物：《Chinese Physics B》 (中国物理B（英文版）)

年 卷 期：2014年第23卷第11期

页      面：496-501页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程（可授工学、理学学位）] 080502[工学-材料学] 

基　　金：supported by the National Basic Research Program of China(Grant No.2011CBA00606) the National Natural Science Foundation of China(Grant Nos.61334002,61106106,and 61176130) the Fundamental Research Fund for the Central Universities of China(Grant No.JB140415) 

主　　题：negative bias temperature instability (NBTI) gate length degradation 

摘      要：The influence of PMOSFET gate length on the parameter degradation relations under negative bias temperature insta- bility （NBTI） stress is studied. The threshold voltage degradation increases with reducing the gate length. By calculating the relations between the threshold voltage and the linear/saturation drain current, we obtain their correlation coefficients. Comparing the test result with the calculated linear/saturation current value, we obtain the ratio factors. The ratio factors decrease differently when the gate length diminishes. When the gate length reduces to some degree, the linear ratio factor decreases from greater than 1 to nearly 1, but the saturation factor decreases from greater than l to smaller than 1. This results from the influence of mobility and the velocity saturation effect. Moreover, due to the un-uniform distribution of potential damages along the channel, the descending slopes of the curve are different.