Towards functional verifying a family of SystemC TLMs
作者机构：College of ComputerNational University of Defense TechnologyChangsha 410073China Laboratory of Software Engineering for Complex SystemsChangsha 410073China Jiangnan Institute of Computing TechnologyWuxi 214083China
出 版 物：《Frontiers of Computer Science》 (中国计算机科学前沿（英文版）)
年 卷 期：2020年第14卷第1期
页 面：53-66页
核心收录：
学科分类：08[工学] 0835[工学-软件工程] 081202[工学-计算机软件与理论] 0812[工学-计算机科学与技术（可授工学、理学学位）]
基 金：The work was supported by the National Key R&D Program of China(2018YFB1004202) by Laboratory of Software Engineering for Complex Systems
主 题：system-on-a-chip transaction level model SystemC feature-oriented functional verification
摘 要：It is often the case that in the development of a system-on-a-chip(SoC)design,a family of SystemC transaction level models(TLM)is *** in the same family often share common functionalities but differ in their timing,implementation,configuration and performance in various SoC developing *** most cases,all the TLMs in a family must be verified for the follow-up design *** our previous work,we proposed to call such family TLM product line(TPL),and proposed feature-oriented(FO)design methodology for efficient TPL ***,developers can only verify TLM in a family one by one,which causes large portion of duplicated verification ***,in our proposed methodology,functional verification of TPL has become a *** this paper,we proposed a novel TPL verification method for FO *** our method,for the given property,we can exponentially reduce the number of TLMs to be verified by identifying mutefeature-modules(MFM),which will avoid duplicated *** proposed method is presented in informal and formal way,and the correctness of it is *** theoretical analysis and experimental results on a real design show the correctness and efficiency of the proposed method.
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