A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner

作     者：高茁 杨宗仁 赵莹 杨袆 张璐 黄令仪 胡伟武 

作者机构：Institute of Computing Technology Chinese Academy of Sciences Graduate University of the Chinese Academy of Sciences 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2009年第30卷第4期

页      面：106-112页

核心收录：

学科分类：0810[工学-信息与通信工程] 08[工学] 081001[工学-通信与信息系统] 

基　　金：supported by the State Key Development Program for Basic Research of China (No. 2005CB321600) the National High Technol-ogy Development Research and Program of China (No. 2008AA110901) the National Natural Science Foundation of China (Nos.60801045, 60803029, 60673146, 60603049) the Beijing Natural Science Foundation (No. 4072024) 

主　　题：serial link receiver CDR equalizer 

摘      要：This paper presents the design of a 10 Gb/s low power wire-line receiver in the 65 nm CMOS process with 1 V supply voltage. The receiver occupies 300×500 μm2. With the novel half rate period calibration clock data recovery （CDR） circuit, the receiver consumes 52 mW power. The receiver can compensate a wide range of channel loss by combining the low power wideband programmable continuous time linear equalizer （CTLE） and decision feedback equalizer （DFE）.