Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET

作     者：Ashwani K.Rana Narottam Chand Vinod Kapoor 

作者机构：Department of Electronics and CommunicationNational Institute of Technology Department of Computer Science and EngineeringNational Institute of Technology 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2011年第32卷第7期

页      面：14-19页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0808[工学-电气工程] 080803[工学-高电压与绝缘技术] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程（可授工学、理学学位）] 080502[工学-材料学] 

主　　题：gate tunneling current analytical model spacer dielectrics DIBL subthreshold slope 

摘      要：A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first *** gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D（source/drain） *** is found that an optimal source/drain-to-gate non-overlapped and high-A：spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped ***,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering（DIBL） *** is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.