Performance Evaluation and Improvement of Chipset Assembly & Test Production Line Based on Variability

作     者：Chang-Jun Li Zong-Shi Xie Xin-Ran Peng Bo Li 

作者机构：School of Aeronautics and AstronauticsUniversity of Electronic Science and Technology of China 

出 版 物：《International Journal of Automation and computing》 (国际自动化与计算杂志（英文版）)

年 卷 期：2019年第16卷第2期

页      面：186-198页

核心收录：

学科分类：12[管理学] 1201[管理学-管理科学与工程(可授管理学、工学学位)] 08[工学] 0802[工学-机械工程] 0701[理学-数学] 0811[工学-控制科学与工程] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：supported by National Natural Science Foundation of China (No. 71671026) Sichuan Science and Technology Program (Nos. 2018GZ0306 and 2017GZ0034) 

主　　题：Performance evaluation and improvement chipset assembly & test production line (CATPL) parameters Little's law variability 

摘      要：Factory physics principles provided a method to evaluate the performance of a simple production line, whose fundamental parameters are known or given. However, it is difficult to obtain the exact and reasonable parameters in actual manufacturing environment, especially for the complex chipset assembly & test production line(CATPL). Besides, research in this field tends to focus on evaluation and improvement of CATPL without considering performance interval and status with variability level. A developed internal benchmark method is proposed, which established three-parameter method based on the Little′s law. It integrates the variability factors, such as processing time, random failure time, and random repair time, to meet performance evaluation and improvement. A case study in a chipset assembly and test factory for the performance of CATPL is implemented. The results demonstrate the potential of the proposed method to meet performance evaluation and emphasise its relevance for practical applications.