Device and circuit analysis of a sub 20 nm double gate MOSFET with gate stack using a look-up-table-based approach

作     者：S Chakraborty A Dasgupta R Das M Kar A Kundu C K Sarkar 

作者机构：Department of Electronics and Communications Engineering Heritage Institute of TechnologyKolkata 700107India Nano Device Simulation LaboratoryDepartment of Electronics and Telecommunication EngineeringJadavpur UniversityKolkata 700032India 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2017年第38卷第12期

页      面：37-41页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程（可授工学、理学学位）] 080502[工学-材料学] 0703[理学-化学] 0702[理学-物理学] 

主　　题：14 nm double gate MOSFET look-up table VerilogA 

摘      要：In this paper, we explore the possibility of mapping devices designed in TCAD environment to its modeled version developed in cadence virtuoso environment using a look-up table （LUT） approach. Circuit simu- lation of newly designed devices in TCAD environment is a very slow and tedious process involving complex scripting. Hence, the LUT based modeling approach has been proposed as a faster and easier alternative in ca- dence environment. The LUTs are prepared by extracting data from the device characteristics obtained from device simulation in TCAD. A comparative study is shown between the TCAD simulation and the LUT-based alternative to showcase the accuracy of modeled devices. Finally the look-up table approach is used to evaluate the perform- ance of circuits implemented using 14 nm nMOSFET.