Optimized stateful material implication logic for three- dimensional data manipulation

作     者：Gina C. Adam Brian D. Hoskins Mirko Prezioso Dmitri B. Strukov 

作者机构：Electrical and Computer Engineering Department University of California Santa Barbara Santa Barbara CA 93106 USA Materials Department University of California Santa Barbara Santa Barbara CA 93106 USA 

出 版 物：《Nano Research》 (纳米研究（英文版）)

年 卷 期：2016年第9卷第12期

页      面：3914-3923页

核心收录：

学科分类：0810[工学-信息与通信工程] 080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 080401[工学-精密仪器及机械] 0804[工学-仪器科学与技术] 080402[工学-测试计量技术及仪器] 0835[工学-软件工程] 081002[工学-信号与信息处理] 

基　　金：supported by the AFOSR under the MURI DARPA the Department of State under the International Fulbright Science and Technology Award 

主　　题：material implication logic memristor resistive random-accessmemory (ReRAM) three-dimensionalintegration 

摘      要：The monolithic three-dimensional integration of memory and logic circuits could dramatically improve the performance and energy efficiency of computing systems. Some conventional and emerging memories are suitable for vertical integration, including highly scalable metal-oxide resistive switching devices （＂memristors＂）. However, the integration of logic circuits has proven to be much more challenging than expected. In this study, we demonstrated memory and logic functionality in a monolithic three-dimensional circuit by adapting the recently proposed memristor-based stateful material implication logic. By modifying the original circuit to increase its robustness to device imperfections, we experimentally showed, for the first time, a reliable multi-cycle multi-gate material implication logic operation and half-adder circuit within a three- dimensional stack of monolithically integrated memristors. Direct data manipulation in three dimensions enables extremely compact and high-throughput logic- in-memory computing and, remarkably, presents a viable solution for the Feynman Grand Challenge of implementing an 8-bit adder at the nanoscale.