Simulation of Gate-All-Around Cylindrical Transistors for Sub-10 Nanometer Scaling

作     者：肖德元 谢志峰 季明华 王曦 俞跃辉 Xiao Deyuan;Xie Joseph;Chi Minhwa;Wang Xi;Yu Yuehui

作者机构：中芯国际集成电路制造(上海)有限公司上海201203 中国科学院上海微系统与信息技术研究所上海200050 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2008年第29卷第3期

页      面：447-457页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程（可授工学、理学学位）] 080502[工学-材料学] 

主　　题：gate-all-around cylindrical transistor device physics TCAD simulation fabrication procedure 

摘      要：A gate-all-around cylindrical （GAAC） transistor for sub-10nm scaling is proposed. The GAAC transistor device physics,TCAD simulation,and proposed fabrication procedure are reported for the first time. Among all other novel FinFET devices, the gate-all-around cylindrical device can be particularly applied for reducing the problems of the conventional multi-gate FinFET and improving the device performance and the scale down capability. According to our simulation,the gate-all-around cylindrical device shows many benefits over conventional multi-gate FinFET, including gate-all- around rectangular （GAAR） devices. With gate-all-around cylindrical architecture,the transistor is controlled by an essen- tially infinite number of gates surrounding the entire cylinder-shaped channel. The electrical integrity within the channel is improved by reducing the leakage current due to the non-symmetrical field accumulation such as the corner effect. The proposed fabrication procedures for devices having GAAC device architecture are also discussed. The method is characterized by its simplicity and full compatibility with conventional planar CMOS technology.