Algorithm and Implementation of Parallel Multiplication in a Mixed Number System
Algorithm and Implementation of Parallel Multiplication in a Mixed Number System作者机构：Institute of Computing Technology Academia Sinica
出 版 物：《Journal of Computer Science and Technology》 (计算机科学技术学报(英文版))
年 卷 期：1988年第3卷第3期
页 面：203-213页
学科分类：07[理学] 0701[理学-数学] 070101[理学-基础数学]
主 题：Algorithm and Implementation of Parallel Multiplication in a Mixed Number System
摘 要：This paper presents a high-speed multiplication algorithm for the mixed number system of the ordinarybinary number and the symmetric redundant binary *** is implemented with the multivalned logictheory,and 3-valued and 2-valued circuits are *** 3-valued circuit proposed in this paper is anemitter-coupled logic circuit with high speed,simplicity and powerful functions.A 3-valued ECL thresholdgate can simultaneously produce six types of one-variable *** array multiplier,designed withthe algorithm and the circuits,is fast and simple,and is suitable for building *** can be used in a high-speed computer just as an ordinary binary multiplier.
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