BIST Design for Detecting Multiple Stuck—Open Faults in CMOS Circuits Using Transition Count

作     者：HafizurRahaman DebeshK.Das 等 

作者机构：IndianInstituteofInformationTechnologyCalcutta－700106India DepartmentofComputerScienceandEngineeringJadavpurUniversityCalcutta－700032India 

出 版 物：《Journal of Computer Science & Technology》 (计算机科学技术学报（英文版）)

年 卷 期：2002年第17卷第6期

页      面：731-737页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

主　　题：BIST CMOS complex cell stuck-open faults testing TPG 

摘      要：This paper presents a built-in self-test (BIST) scheme for detecting allrobustly testable multiple stuck-open faults confined to any single complex cell of a CMOS *** test pattern generator (TPG) generates all n·2~n single-input-change (SIC) ordered test pairsfor an n-input circuit-under-test (CUT) contained in a sequence of length 2n·2~n. The proposeddesign is universal, i.e., independent of the structure and functionality of the CUT. A counter thatcounts the number of alternate transitions at the output of the CUT, is used as a signatureanalyzer (SA). The design of TPG and SA is simple and no special design-or synthesis-for-testabilitytechniques and/or additional control lines are needed.