Litho-Asym Vnet: super-resolution lithography modeling with an asymmetric V-net architecture

作     者：Qing ZHANG Yuhang ZHANG Wei LU Huajie HUANG Zheng ZHONG Congshu ZHOU Yongfu LI Qing ZHANG;Yuhang ZHANG;Wei LU;Huajie HUANG;Zheng ZHONG;Congshu ZHOU;Yongfu LI

作者机构：Department of Micro-Nano Electronics and Mo E Key Lab of Artificial IntelligenceShanghai Jiao Tong University Primarius Technologies Co.Ltd. 

出 版 物：《Science China(Information Sciences)》 (中国科学:信息科学(英文版))

年 卷 期：2023年第66卷第12期

页      面：301-302页

核心收录：

学科分类：0303[法学-社会学] 080903[工学-微电子学与固体电子学] 070207[理学-光学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程（可授工学、理学学位）] 080502[工学-材料学] 0702[理学-物理学] 

基　　金：supported by National Natural Science Foundation of China (Grant Nos. 62141414  62350610271) 

主　　题：Optical resolving power 

摘      要：Lithography simulation is key to the preparation of mask data and verification of mask patterns [1], which enhances design-to-wafer fidelity and minimizes distortions. However,the complexity of lithography simulation has tremendously increased with the decrease in feature size, prolonging the simulation cycle. Hence, an accurate and fast lithography simulation is in great demand.