Toward monolithic growth integration of nanowire electronics in 3D architecture: a review

作     者：Lei LIANG Ruijin HU Linwei YU 

作者机构：School of Electronic Science and Engineering Nanjing University School of Physical Science and Technology/Microelectronics Industry Research Institute Yangzhou University 

出 版 物：《Science China(Information Sciences)》 (中国科学:信息科学(英文版))

年 卷 期：2023年第66卷第10期

页      面：105-134页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 07[理学] 070205[理学-凝聚态物理] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程（可授工学、理学学位）] 080502[工学-材料学] 0702[理学-物理学] 

基　　金：supported by National Key Research Program of China (Grant Nos. 92164201 61921005) National Natural Science Foundation of China (Grant Nos. 61974064 11874198) Micro-fabrication and Integration Technology Center of Nanjing University 

主　　题：catalytic growth silicon nanowires electronics monolithic 3D-integration 

摘      要：Quasi-one-dimensional(1D) semiconducting nanowires(NWs), with excellent electrostatic control capability, are widely regarded as advantageous channels for the fabrication of high-performance microelectronics, memories, and sensors. For example, the latest Si field-effect-transistor(FET) technology nodes,N5 nm, use horizontally-stacked SiNWs or nanosheet channels in a gate-all-around(GAA) ***, further scaling of the top-down etching fabrication is reaching physical limits, necessitating the development of new fabrication or integration technologies in monolithic three dimensional(3D) architecture to push Moore’s law forward. These new capabilities are also critical, for implementing of more advanced non von Neumann paradigms of in-memory and neuromorphic computing. For this, a versatile and highly controllable low-temperature growth integration of orderly 1D SiNW channels is desired, as it will provide an alternative or complementary new route to fabricate a multilayer of Si CMOS logics/memories in a fully 3D stacked manner. In this study, we assess the evolution and recent progress of catalytic growth strategies for ultrathin 1D channels in-plane or planar NWs, and revisit the key mechanisms and technological milestones in geometry, lattice quality, line-shape, position, and composition controls. We aim to eventually establish a reliable catalytic growth integration strategy, suitable for the fabrication of GAA FETs and the implementation of a monolithic 3D integration architecture. Finally, we also present a summary and perspectives on the current challenges and future opportunities of monolithic growth integration of NW electronics in 3D architecture.