3.3 kV 4H-SiC DMOSFET with a source-contacted dummy gate for high-frequency applications

作     者：Kyuhyun Cha Kwangsoo Kim Kyuhyun Cha;Kwangsoo Kim

作者机构：Department of Electronic EngineeringSogang UniversitySeoul 04107Korea 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2021年第42卷第6期

页      面：41-47页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程（可授工学、理学学位）] 080502[工学-材料学] 

基　　金：supported by the MSIT(Ministry of Science and ICT) Korea under the ITRC(Information Technology Research Center)support program(IITP-2020-2018-0-01421)supervised by the IITP(Institute for Information&Communications Technology Planning&Evaluation) 

主　　题：4H-Si C MOSFET dummy-gate gate-drain charge switching loss 

摘      要：In this paper,a 4 H-Si C DMOSFET with a source-contacted dummy gate(DG-MOSFET)is proposed and analyzed through Sentaurus TCAD and PSIM *** source-contacted MOS structure forms fewer depletion regions than the PN ***,the overlapping region between the gate and the drain can be significantly reduced while limiting RON *** a result,the DG-MOSFET offers an improved high-frequency figure of merit(HF-FOM)over the conventional DMOSFET(C-MOSFET)and central-implant MOSFET(CI-MOSFET).The HF-FOM(RON×QGD)of the DG-MOSFET was improved by59.2%and 22.2%compared with those of the C-MOSFET and CI-MOSFET,*** a double-pulse test,the DG-MOSFET could save total power losses of 53.4%and 5.51%,***,in a power circuit simulation,the switching power loss was reduced by 61.9%and 12.7%in a buck converter and 61%and 9.6%in a boost converter.