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Device physics and design of FD-SOI JLFET with step-gate-oxide structure to suppress GIDL effect

有 step-gate-oxide 的 FD-SOI JLFET 的设备物理和设计组织压制 GIDL 效果*

作     者:Bin Wang Xin-Long Shi Yun-Feng Zhang Yi Chen Hui-Yong Hu Li-Ming Wang 王斌;史鑫龙;张云峰;陈伊;胡辉勇;王利明

作者机构:State Key Discipline Laboratory of Wide Bandgap Semiconductor TechnologySchool of MicroelectronicsXidian UniversityXi'an 710071China Mailbox 150BaoJi 721000China 

出 版 物:《Chinese Physics B》 (中国物理B(英文版))

年 卷 期:2021年第30卷第4期

页      面:497-501页

核心收录:

学科分类:080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术(可授工学、理学学位)] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程(可授工学、理学学位)] 080502[工学-材料学] 

基  金:Project supported by the National Natural Science Foundation of China(Grant No.61704130) the Fund from the Science and Technology on Analog Integrated Circuit Laboratory,China(Grant No.JCKY2019210C029) 

主  题:junctionless field-effect transistor(FET) gate-induced drain leakage(GIDL) step-gate-oxide offstate current 

摘      要:A novel n-type junctionless field-effect transistor(JLFET) with a step-gate-oxide(SGO) structure is proposed to suppress the gate-induced drain leakage(GIDL) effect and off-state current I_(off).Introducing a 6-nm-thick tunnel-gateoxide and maintaining 3-nm-thick control-gate-oxide,lateral band-to-band tunneling(L-BTBT) width is enlarged and its tunneling probability is reduced at the channel-drain surface,leading the off-state current I_(off) to decrease ***,the thicker tunnel-gate-oxide can reduce the influence on the total gate capacitance of JLFET,which could alleviate the capacitive load of the transistor in the circuit *** simulation shows that I_(off) of the new optimized JLFET reduced significantly with little impaction on its on-state current Ion and threshold voltage V_(TH) becoming less,thus showing an improved I_(on)/I_(off) ratio(5×10^(4)) and subthreshold swing(84 mV/dec),compared with the scenario of the normal *** influence of the thickness and length of SGO structure on the performance of JLFET are discussed in detail,which could provide useful instruction for the device design.

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