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A 3.96 GHz phase-locked loop for mode-1 MB-OFDM UWB hopping carrier generation

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Journal of Semiconductors 2009年第7期30卷 91-95页

作者：郑永正李伟男夏玲琍黄煜梅洪志良 State Key laboratory of asic & System Fudan University

A fully integrated phase-locked loop（PLL） is presented for a single quadrature output frequency of 3.96 *** proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier *** adaptive frequency calibration loop is incorporated into the *** capacitance area in the loop filter is largely reduced through a capacitor *** in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm2 die *** results show that the PLL achieves a phase noise of-70 dBc/Hz at 10 kHz offset and-113 dBc/Hz at 1 MHz *** integrated RMS jitter from 1 kHz to 10 MHz is 2.2 *** reference spur level is less than-68 dBc.

关键词： phase-locked loop adaptive frequency calibration loop filter CMOS UWB

All-CMOS temperature compensated current reference

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Journal of Semiconductors 2010年第6期31卷 157-160页

作者：赵喆周锋黄圣专 State Key laboratory of asic & System Fudan University

This paper presents a novel temperature independent current reference based on the theory of mutual compensation of mobility and threshold *** is completely compatible with standard *** experiment results indicate that the temperature coefficient of this current reference is less than 290 ppm/℃over a temperature range from-20 to 110℃.

关键词： CMOS integrated circuits current reference temperature compensation

A low noise CMOS RF front-end for UWB 6-9 GHz applications

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Journal of Semiconductors 2010年第11期31卷 113-117页

作者：周锋高亭兰飞李巍李宁任俊彦 State Key laboratory of asic & System Fudan University

An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented.A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13μm RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB,an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of-12.6 dBm while in the low gain *** RF front-end consumes 17 mA from a 1.2 V supply voltage.

关键词： CMOS ultra-wideband resistive feedback low noise amplifier folded quadrature mixer noise figure linearity

A low power 3-5 GHz CMOS UWB receiver front-end

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Journal of Semiconductors 2009年第3期30卷 109-113页

作者：李伟男黄煜梅洪志良 State Key laboratory of asic & System Fudan University

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm^2.

关键词： UWB direct-conversion receiver low power RF CMOS passive mixer

A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology

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Journal of Semiconductors 2010年第1期31卷 46-50页

作者：陈虎陆波邵轲夏玲琍黄煜梅洪志良 State Key laboratory of asic & System Fudan University

A 4224 MHz phase-locked loop （PLL） is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of-94 dBc/Hz and -114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps （100 Hz to 100 MHz） and the PLL has a reference spur of-63 dB with the second order passive low pass filter.

关键词： PLL in-band noise dynamic mismatch RMS jitter

A novel low-offset dynamic comparator for sub-1-V pipeline ADCs

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Journal of Semiconductors 2011年第8期32卷 93-97页

作者：杨金达王贤彪李立程旭郭亚炜曾晓洋 State Key laboratory of asic and System Fudan University

A novel low-offset dynamic comparator for high-speed low-voltage analog-to-digital converters （ADCs） has been *** the proposed comparator,a CMOS switch takes the place of the dynamic current sources in the differential comparator,which allows the differential input transistors still to operate in the saturation region at the comparing *** gives the proposed comparator a low offset as the differential comparator while tolerating a sub-1-V supply ***,it also features a larger input swing,less sensitivity to common mode voltage,and a simple relationship between the input and reference *** proposed comparator with two traditional comparators has been realized by SMIC 0.13μm CMOS *** contrast experimental results verify these advantages over conventional *** has been used in a 12-bit 100-MS/s pipeline ADC.

关键词： comparator high speed low voltage low offset ADC

A 2.4-GHz low power dual gain low noise amplifier for ZigBee

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Journal of Semiconductors 2009年第7期30卷 109-113页

作者：高佩君闵昊 State Key laboratory of asic & System Fudan University

This paper presents a fully differential dual gain low noise amplifier（DGLNA） for low power 2.45-GHz ZigBee/IEEE 802.15.4 *** effect of input parasitics on the inductively degenerated cascode LNA is *** design details within the guidelines of the analysis are *** chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS *** DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return *** high gain mode, the measured noise figure（NF） is 2.3-3 dB in the whole 2.45-GHz ISM *** measured 1-dB compression point, IIP3 and IIP2 is-9, 1 and 33 dBm, *** DGLNA consumes 2 mA of current from a 1.8 V power supply.

关键词： CMOS low noise amplifier input parasitics low power noise figure ZigBee IEEE 802.15.4

A low jitter,low spur multiphase phase-locked loop for an IR-UWB receiver

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Journal of Semiconductors 2010年第8期31卷 121-125页

作者：邵轲陈虎潘姚华洪志良 State Key laboratory of asic and System Fudan University

A low jitter,low spur multiphase phase-locked loop（PLL） for an impulse radio ultra-wideband（IR-UWB） receiver is *** PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock *** this design,a noise and matching improved voltage-controlled oscillator（VCO） is devised to enhance the timing accuracy and phase noise performance of multiphase *** good matching achieved in the charge pump and careful choice of the loop filter bandwidth,the reference spur is suppressed. A phase noise of-118.42 dBc/Hz at a frequency offset of 1 MHz,RMS jitter of 1.53 ps and reference spur of-66.81 dBc are achieved at a carrier frequency of 264 MHz in *** chip was manufactured in 0.13μm CMOS technology and consumes 4.23 mW from a 1.2 V supply while occupying 0.14 mm^2 area.

关键词： PLL multiphase ring oscillator RMS jitter reference spur IR-UWB

An offset-insensitive switched-capacitor bandgap reference with continuous output

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Journal of Semiconductors 2009年第8期30卷 132-135页

作者：郑鹏严伟张科李文宏 State Key laboratory of asic & System Fudan University

An improved switched-capacitor bandgap reference with a continuous output voltage of 1.26 V has been implemented with Chartered 0.35-μm 5-V CMOS process. The output offset voltage, induced by non-ideal characteristics of operational amplifier and bias current generator, is suppressed by the proposed sample-and-hold circuit and self-bias technique. Experimental results show that the proposed circuit operates properly under a supply voltage varying from 3 to 5 V. The measured temperature coefficient is 112 ppm/℃ and the power supply rejection ratio of output voltage without any filtering capacitor is -40 dB and -33 dB at 100 Hz and 10 MHz, respectively.

关键词： bandgap reference switched-capacitor offset self-bias continuous output